Merge branches 'clks' and 'pnx' into devel

3 files changed, 10 insertions, 5 deletions

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 88f5d71248d9..9d4da6ac28eb 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1068,4 +1068,6 @@ void setup_mm_for_reboot(char mode)
                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
                 flush_pmd_entry(pmd);
         }
+
+        local_flush_tlb_all();
 }
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 395cc90c6613..7a5337ed7d68 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -59,8 +59,6 @@ ENTRY(cpu_v6_proc_fin)
  *      to what would be the reset vector.
  *
  *      - loc   - location to jump to for soft reset
- *
- *      It is assumed that:
  */
         .align  5
 ENTRY(cpu_v6_reset)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3a285218fd15..7aaf88a3b7aa 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -45,7 +45,14 @@ ENTRY(cpu_v7_proc_init)
 ENDPROC(cpu_v7_proc_init)
 
 ENTRY(cpu_v7_proc_fin)
-        mov     pc, lr
+        stmfd   sp!, {lr}
+        cpsid   if                              @ disable interrupts
+        bl      v7_flush_kern_cache_all
+        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
+        bic     r0, r0, #0x1000                 @ ...i............
+        bic     r0, r0, #0x0006                 @ .............ca.
+        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
+        ldmfd   sp!, {pc}
 ENDPROC(cpu_v7_proc_fin)
 
 /*
@@ -56,8 +63,6 @@ ENDPROC(cpu_v7_proc_fin)
  *      to what would be the reset vector.
  *
  *      - loc   - location to jump to for soft reset
- *
- *      It is assumed that:
  */
         .align  5
 ENTRY(cpu_v7_reset)