diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2009-04-30 12:06:15 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-04-30 15:12:59 -0400 |
commit | 855c551f5b8cc3815d58e1056c1f1e7c461e2d24 (patch) | |
tree | c2a84666b3a86c3e5cb5272ed42b802f9411ec33 /arch/arm/mm | |
parent | 7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47 (diff) |
[ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created
This patch adds a workaround for the 458693 Cortex-A8 (r2p0)
erratum. It sets the corresponding bits in the auxiliary control
register so that the PLD instruction becomes a NOP.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r-- | arch/arm/mm/proc-v7.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index fc81159596fe..370baa7a0f08 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -188,6 +188,12 @@ __v7_setup: | |||
188 | orr r10, r10, #(1 << 6) @ set IBE to 1 | 188 | orr r10, r10, #(1 << 6) @ set IBE to 1 |
189 | mcr p15, 0, r10, c1, c0, 1 @ write aux control register | 189 | mcr p15, 0, r10, c1, c0, 1 @ write aux control register |
190 | #endif | 190 | #endif |
191 | #ifdef CONFIG_ARM_ERRATA_458693 | ||
192 | mrc p15, 0, r10, c1, c0, 1 @ read aux control register | ||
193 | orr r10, r10, #(1 << 5) @ set L1NEON to 1 | ||
194 | orr r10, r10, #(1 << 9) @ set PLDNOP to 1 | ||
195 | mcr p15, 0, r10, c1, c0, 1 @ write aux control register | ||
196 | #endif | ||
191 | mov r10, #0 | 197 | mov r10, #0 |
192 | #ifdef HARVARD_CACHE | 198 | #ifdef HARVARD_CACHE |
193 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate | 199 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |