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authorThomas Gleixner <tglx@linutronix.de>2006-07-02 20:21:18 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 20:29:22 -0400
commitbb8d5a55a523869ebcdd004a08ed5fab86b474e3 (patch)
treeb1d9d8785d24ce6feae16390e7b9f697e2ded141 /arch/arm/mm
parent284c66806eb6df7f5c66d298681f1abe81a5a9ab (diff)
[PATCH] ARM: Fixup missing includes in arch/arm/mm/proc-<cputype>.S
For several proc-<cputype>.S files the include of proc-macros.S is missing. Make it compile and work again. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/proc-arm720.S2
-rw-r--r--arch/arm/mm/proc-sa110.S2
-rw-r--r--arch/arm/mm/proc-sa1100.S2
3 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 0e6946ab6e5b..c2f0705bfd49 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -41,6 +41,8 @@
41#include <asm/procinfo.h> 41#include <asm/procinfo.h>
42#include <asm/ptrace.h> 42#include <asm/ptrace.h>
43 43
44#include "proc-macros.S"
45
44/* 46/*
45 * Function: arm720_proc_init (void) 47 * Function: arm720_proc_init (void)
46 * : arm720_proc_fin (void) 48 * : arm720_proc_fin (void)
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index e812246277cf..c878064e9b88 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -23,6 +23,8 @@
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
24#include <asm/ptrace.h> 24#include <asm/ptrace.h>
25 25
26#include "proc-macros.S"
27
26/* 28/*
27 * the cache line size of the I and D cache 29 * the cache line size of the I and D cache
28 */ 30 */
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index ba32cc6296a0..b23b66a6155a 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -27,6 +27,8 @@
27#include <asm/pgtable-hwdef.h> 27#include <asm/pgtable-hwdef.h>
28#include <asm/pgtable.h> 28#include <asm/pgtable.h>
29 29
30#include "proc-macros.S"
31
30/* 32/*
31 * the cache line size of the I and D cache 33 * the cache line size of the I and D cache
32 */ 34 */