[ARM] 5227/1: Add the ENDPROC declarations to the .S files

This declaration specifies the "function" type and size for various
assembly functions, mainly needed for generating the correct branch
instructions in Thumb-2.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

5 files changed, 22 insertions, 0 deletions

diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
index eb90bce38e14..2e6dc040c654 100644
--- a/arch/arm/mm/abort-ev7.S
+++ b/arch/arm/mm/abort-ev7.S
@@ -30,3 +30,4 @@ ENTRY(v7_early_abort)
          * New designs should not need to patch up faults.
          */
         mov     pc, lr
+ENDPROC(v7_early_abort)
diff --git a/arch/arm/mm/abort-nommu.S b/arch/arm/mm/abort-nommu.S
index a7cc7f9ee45d..625e580945b5 100644
--- a/arch/arm/mm/abort-nommu.S
+++ b/arch/arm/mm/abort-nommu.S
@@ -17,3 +17,4 @@ ENTRY(nommu_early_abort)
         mov     r0, #0                          @ clear r0, r1 (no FSR/FAR)
         mov     r1, #0
         mov     pc, lr
+ENDPROC(nommu_early_abort)
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 35ffc4d95997..d19c2bec2b1f 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -66,6 +66,7 @@ finished:
         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
         isb
         mov     pc, lr
+ENDPROC(v7_flush_dcache_all)
 
 /*
  *      v7_flush_cache_all()
@@ -85,6 +86,7 @@ ENTRY(v7_flush_kern_cache_all)
         mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
         ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
         mov     pc, lr
+ENDPROC(v7_flush_kern_cache_all)
 
 /*
  *      v7_flush_cache_all()
@@ -110,6 +112,8 @@ ENTRY(v7_flush_user_cache_all)
  */
 ENTRY(v7_flush_user_cache_range)
         mov     pc, lr
+ENDPROC(v7_flush_user_cache_all)
+ENDPROC(v7_flush_user_cache_range)
 
 /*
  *      v7_coherent_kern_range(start,end)
@@ -155,6 +159,8 @@ ENTRY(v7_coherent_user_range)
         dsb
         isb
         mov     pc, lr
+ENDPROC(v7_coherent_kern_range)
+ENDPROC(v7_coherent_user_range)
 
 /*
  *      v7_flush_kern_dcache_page(kaddr)
@@ -174,6 +180,7 @@ ENTRY(v7_flush_kern_dcache_page)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_flush_kern_dcache_page)
 
 /*
  *      v7_dma_inv_range(start,end)
@@ -202,6 +209,7 @@ ENTRY(v7_dma_inv_range)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_dma_inv_range)
 
 /*
  *      v7_dma_clean_range(start,end)
@@ -219,6 +227,7 @@ ENTRY(v7_dma_clean_range)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_dma_clean_range)
 
 /*
  *      v7_dma_flush_range(start,end)
@@ -236,6 +245,7 @@ ENTRY(v7_dma_flush_range)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_dma_flush_range)
 
         __INITDATA
 
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b49f9a4c82c8..dff967784626 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -25,9 +25,11 @@
 
 ENTRY(cpu_v7_proc_init)
         mov     pc, lr
+ENDPROC(cpu_v7_proc_init)
 
 ENTRY(cpu_v7_proc_fin)
         mov     pc, lr
+ENDPROC(cpu_v7_proc_fin)
 
 /*
  *      cpu_v7_reset(loc)
@@ -43,6 +45,7 @@ ENTRY(cpu_v7_proc_fin)
         .align  5
 ENTRY(cpu_v7_reset)
         mov     pc, r0
+ENDPROC(cpu_v7_reset)
 
 /*
  *      cpu_v7_do_idle()
@@ -54,6 +57,7 @@ ENTRY(cpu_v7_reset)
 ENTRY(cpu_v7_do_idle)
         .long   0xe320f003                      @ ARM V7 WFI instruction
         mov     pc, lr
+ENDPROC(cpu_v7_do_idle)
 
 ENTRY(cpu_v7_dcache_clean_area)
 #ifndef TLB_CAN_READ_FROM_L1_CACHE
@@ -65,6 +69,7 @@ ENTRY(cpu_v7_dcache_clean_area)
         dsb
 #endif
         mov     pc, lr
+ENDPROC(cpu_v7_dcache_clean_area)
 
 /*
  *      cpu_v7_switch_mm(pgd_phys, tsk)
@@ -89,6 +94,7 @@ ENTRY(cpu_v7_switch_mm)
         isb
 #endif
         mov     pc, lr
+ENDPROC(cpu_v7_switch_mm)
 
 /*
  *      cpu_v7_set_pte_ext(ptep, pte)
@@ -141,6 +147,7 @@ ENTRY(cpu_v7_set_pte_ext)
         mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
 #endif
         mov     pc, lr
+ENDPROC(cpu_v7_set_pte_ext)
 
 cpu_v7_name:
         .ascii  "ARMv7 Processor"
@@ -188,6 +195,7 @@ __v7_setup:
         bic     r0, r0, r5                      @ clear bits them
         orr     r0, r0, r6                      @ set them
         mov     pc, lr                          @ return to head.S:__ret
+ENDPROC(__v7_setup)
 
         /*
          *         V X F   I D LR
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index b56dda8052f7..24ba5109f2e7 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -51,6 +51,7 @@ ENTRY(v7wbi_flush_user_tlb_range)
         mcr     p15, 0, ip, c7, c5, 6           @ flush BTAC/BTB
         dsb
         mov     pc, lr
+ENDPROC(v7wbi_flush_user_tlb_range)
 
 /*
  *      v7wbi_flush_kern_tlb_range(start,end)
@@ -77,6 +78,7 @@ ENTRY(v7wbi_flush_kern_tlb_range)
         dsb
         isb
         mov     pc, lr
+ENDPROC(v7wbi_flush_kern_tlb_range)
 
         .section ".text.init", #alloc, #execinstr