[ARM SMP] Add Realview MPcore SMP support

Add SMP support for the MPcore tile fitted to the Realview ARM
platform.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 18 insertions, 0 deletions

diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index a39d8fa2ede5..92f3ca31b7b9 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -12,6 +12,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/hardware/arm_scu.h>
 #include <asm/procinfo.h>
 #include <asm/pgtable.h>
 
@@ -194,6 +195,23 @@ cpu_v6_name:
  *      - cache type register is implemented
  */
 __v6_setup:
+#ifdef CONFIG_SMP
+        /* Set up the SCU on core 0 only */
+        mrc     p15, 0, r0, c0, c0, 5           @ CPU core number
+        ands    r0, r0, #15
+        moveq   r0, #0x10000000 @ SCU_BASE
+        orreq   r0, r0, #0x00100000
+        ldreq   r5, [r0, #SCU_CTRL]
+        orreq   r5, r5, #1
+        streq   r5, [r0, #SCU_CTRL]
+
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+        mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
+        orr     r0, r0, #0x20
+        mcr     p15, 0, r0, c1, c0, 1
+#endif
+#endif
+
         mov     r0, #0
         mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache