aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mm
diff options
context:
space:
mode:
authorNicolas Pitre <nico@cam.org>2008-11-08 15:15:53 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-11-08 18:08:54 -0500
commit72bc2b1ad62f4d2f0a51b35829093d41f55accce (patch)
tree56a6c8db69e4835259ba135c721a28b3a91ba4ed /arch/arm/mm
parent4bab0ea1d42dd1927af9df6fbf0003fc00617c50 (diff)
[ARM] 5329/1: Feroceon: fix feroceon_l2_inv_range
Same fix as commit c7cf72dcadb: when 'start' and 'end' are less than a cacheline apart and 'start' is unaligned we are done after cleaning and invalidating the first cacheline. Cc: <stable@kernel.org> Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/cache-feroceon-l2.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 13cdae8b0d44..80cd207cbaea 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -150,7 +150,7 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
150 /* 150 /*
151 * Clean and invalidate partial last cache line. 151 * Clean and invalidate partial last cache line.
152 */ 152 */
153 if (end & (CACHE_LINE_SIZE - 1)) { 153 if (start < end && end & (CACHE_LINE_SIZE - 1)) {
154 l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); 154 l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
155 end &= ~(CACHE_LINE_SIZE - 1); 155 end &= ~(CACHE_LINE_SIZE - 1);
156 } 156 }
@@ -158,7 +158,7 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
158 /* 158 /*
159 * Invalidate all full cache lines between 'start' and 'end'. 159 * Invalidate all full cache lines between 'start' and 'end'.
160 */ 160 */
161 while (start != end) { 161 while (start < end) {
162 unsigned long range_end = calc_range_end(start, end); 162 unsigned long range_end = calc_range_end(start, end);
163 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); 163 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
164 start = range_end; 164 start = range_end;