[ARM] nommu: manage the CP15 things

All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:

     Related operation	Safe condition
  a. any CP15 access	!CPU_CP15
  b. alignment trap	CPU_CP15_MMU
  c. D-cache(C-bit)	CPU_CP15
  d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
				CPU_ARM720 || CPU_ARM740 ||
				CPU_XSCALE || CPU_XSC3 )
  e. alternate vector	CPU_CP15 && !CPU_ARM740
  f. TTB		CPU_CP15_MMU
  g. Domain		CPU_CP15_MMU
  h. FSR/FAR		CPU_CP15_MMU

For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

2 files changed, 14 insertions, 4 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c7fb835c148c..0ac11ea84508 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -445,15 +445,15 @@ config CPU_BIG_ENDIAN
           of your chipset/board/processor.
 
 config CPU_ICACHE_DISABLE
-        bool "Disable I-Cache"
-        depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
+        bool "Disable I-Cache (I-bit)"
+        depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
         help
           Say Y here to disable the processor instruction cache. Unless
           you have a reason not to or are unsure, say N.
 
 config CPU_DCACHE_DISABLE
-        bool "Disable D-Cache"
-        depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
+        bool "Disable D-Cache (C-bit)"
+        depends on CPU_CP15
         help
           Say Y here to disable the processor data cache. Unless
           you have a reason not to or are unsure, say N.
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index b8ad5d58ebe2..b2908063ed6a 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -29,9 +29,13 @@ ENTRY(v4_flush_user_cache_all)
  *      Clean and invalidate the entire cache.
  */
 ENTRY(v4_flush_kern_cache_all)
+#ifdef CPU_CP15
         mov     r0, #0
         mcr     p15, 0, r0, c7, c7, 0           @ flush ID cache
         mov     pc, lr
+#else
+        /* FALLTHROUGH */
+#endif
 
 /*
  *      flush_user_cache_range(start, end, flags)
@@ -44,9 +48,13 @@ ENTRY(v4_flush_kern_cache_all)
  *      - flags - vma_area_struct flags describing address space
  */
 ENTRY(v4_flush_user_cache_range)
+#ifdef CPU_CP15
         mov     ip, #0
         mcreq   p15, 0, ip, c7, c7, 0           @ flush ID cache
         mov     pc, lr
+#else
+        /* FALLTHROUGH */
+#endif
 
 /*
  *      coherent_kern_range(start, end)
@@ -108,8 +116,10 @@ ENTRY(v4_dma_inv_range)
  *      - end    - virtual end address
  */
 ENTRY(v4_dma_flush_range)
+#ifdef CPU_CP15
         mov     r0, #0
         mcr     p15, 0, r0, c7, c7, 0           @ flush ID cache
+#endif
         /* FALLTHROUGH */
 
 /*