ARM: pm: add generic CPU suspend/resume support

This adds core support for saving and restoring CPU coprocessor
registers for suspend/resume support.  This contains support for suspend
with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
Tested on Assabet and Tegra 2.

Tested-by: Colin Cross <ccross@android.com>
Tested-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

24 files changed, 393 insertions, 33 deletions

diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index bcf748d9f4e2..226e3d8351c2 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -493,6 +493,9 @@ arm1020_processor_functions:
         .word   cpu_arm1020_dcache_clean_area
         .word   cpu_arm1020_switch_mm
         .word   cpu_arm1020_set_pte_ext
+        .word   0
+        .word   0
+        .word   0
         .size   arm1020_processor_functions, . - arm1020_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index ab7ec26657ea..86d9c2cf0bce 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -474,6 +474,9 @@ arm1020e_processor_functions:
         .word   cpu_arm1020e_dcache_clean_area
         .word   cpu_arm1020e_switch_mm
         .word   cpu_arm1020e_set_pte_ext
+        .word   0
+        .word   0
+        .word   0
         .size   arm1020e_processor_functions, . - arm1020e_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 831c5e54e22f..83d3dd34f846 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -457,6 +457,9 @@ arm1022_processor_functions:
         .word   cpu_arm1022_dcache_clean_area
         .word   cpu_arm1022_switch_mm
         .word   cpu_arm1022_set_pte_ext
+        .word   0
+        .word   0
+        .word   0
         .size   arm1022_processor_functions, . - arm1022_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index e3f7e9a166bf..686043ee7281 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -452,6 +452,9 @@ arm1026_processor_functions:
         .word   cpu_arm1026_dcache_clean_area
         .word   cpu_arm1026_switch_mm
         .word   cpu_arm1026_set_pte_ext
+        .word   0
+        .word   0
+        .word   0
         .size   arm1026_processor_functions, . - arm1026_processor_functions
 
         .section .rodata
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 6a7be1863edd..5f79dc4ce3fb 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -284,6 +284,9 @@ ENTRY(arm6_processor_functions)
                 .word   cpu_arm6_dcache_clean_area
                 .word   cpu_arm6_switch_mm
                 .word   cpu_arm6_set_pte_ext
+                .word   0
+                .word   0
+                .word   0
                 .size   arm6_processor_functions, . - arm6_processor_functions
 
 /*
@@ -301,6 +304,9 @@ ENTRY(arm7_processor_functions)
                 .word   cpu_arm7_dcache_clean_area
                 .word   cpu_arm7_switch_mm
                 .word   cpu_arm7_set_pte_ext
+                .word   0
+                .word   0
+                .word   0
                 .size   arm7_processor_functions, . - arm7_processor_functions
 
                 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index c285395f44b2..665266da143c 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -185,6 +185,9 @@ ENTRY(arm720_processor_functions)
                 .word   cpu_arm720_dcache_clean_area
                 .word   cpu_arm720_switch_mm
                 .word   cpu_arm720_set_pte_ext
+                .word   0
+                .word   0
+                .word   0
                 .size   arm720_processor_functions, . - arm720_processor_functions
 
                 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 38b27dcba727..6f9d12effee1 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -130,6 +130,9 @@ ENTRY(arm740_processor_functions)
         .word   cpu_arm740_dcache_clean_area
         .word   cpu_arm740_switch_mm
         .word   0                       @ cpu_*_set_pte
+        .word   0
+        .word   0
+        .word   0
         .size   arm740_processor_functions, . - arm740_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 0c9786de20af..e4c165ca6696 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -70,6 +70,9 @@ ENTRY(arm7tdmi_processor_functions)
                 .word   cpu_arm7tdmi_dcache_clean_area
                 .word   cpu_arm7tdmi_switch_mm
                 .word   0               @ cpu_*_set_pte
+                .word   0
+                .word   0
+                .word   0
                 .size   arm7tdmi_processor_functions, . - arm7tdmi_processor_functions
 
                 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 6109f278a904..219980ec8b6e 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -387,6 +387,40 @@ ENTRY(cpu_arm920_set_pte_ext)
 #endif
         mov     pc, lr
 
+/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
+.globl  cpu_arm920_suspend_size
+.equ    cpu_arm920_suspend_size, 4 * 3
+#ifdef CONFIG_PM
+ENTRY(cpu_arm920_do_suspend)
+        stmfd   sp!, {r4 - r7, lr}
+        mrc     p15, 0, r4, c13, c0, 0  @ PID
+        mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
+        mrc     p15, 0, r6, c2, c0, 0   @ TTB address
+        mrc     p15, 0, r7, c1, c0, 0   @ Control register
+        stmia   r0, {r4 - r7}
+        ldmfd   sp!, {r4 - r7, pc}
+ENDPROC(cpu_arm920_do_suspend)
+
+ENTRY(cpu_arm920_do_resume)
+        mov     ip, #0
+        mcr     p15, 0, ip, c8, c7, 0   @ invalidate I+D TLBs
+        mcr     p15, 0, ip, c7, c7, 0   @ invalidate I+D caches
+        ldmia   r0, {r4 - r7}
+        mcr     p15, 0, r4, c13, c0, 0  @ PID
+        mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
+        mcr     p15, 0, r6, c2, c0, 0   @ TTB address
+        mov     r0, r7                  @ control register
+        mov     r2, r6, lsr #14         @ get TTB0 base
+        mov     r2, r2, lsl #14
+        ldr     r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
+                     PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
+        b       cpu_resume_mmu
+ENDPROC(cpu_arm920_do_resume)
+#else
+#define cpu_arm920_do_suspend   0
+#define cpu_arm920_do_resume    0
+#endif
+
         __CPUINIT
 
         .type   __arm920_setup, #function
@@ -432,6 +466,9 @@ arm920_processor_functions:
         .word   cpu_arm920_dcache_clean_area
         .word   cpu_arm920_switch_mm
         .word   cpu_arm920_set_pte_ext
+        .word   cpu_arm920_suspend_size
+        .word   cpu_arm920_do_suspend
+        .word   cpu_arm920_do_resume
         .size   arm920_processor_functions, . - arm920_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index bb2f0f46a5e6..36154b1e792a 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -436,6 +436,9 @@ arm922_processor_functions:
         .word   cpu_arm922_dcache_clean_area
         .word   cpu_arm922_switch_mm
         .word   cpu_arm922_set_pte_ext
+        .word   0
+        .word   0
+        .word   0
         .size   arm922_processor_functions, . - arm922_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index c13e01accfe2..89c5e0009c4c 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -503,6 +503,9 @@ arm925_processor_functions:
         .word   cpu_arm925_dcache_clean_area
         .word   cpu_arm925_switch_mm
         .word   cpu_arm925_set_pte_ext
+        .word   0
+        .word   0
+        .word   0
         .size   arm925_processor_functions, . - arm925_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 42eb4315740b..6a4bdb2c94a7 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -401,6 +401,40 @@ ENTRY(cpu_arm926_set_pte_ext)
 #endif
         mov     pc, lr
 
+/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
+.globl  cpu_arm926_suspend_size
+.equ    cpu_arm926_suspend_size, 4 * 3
+#ifdef CONFIG_PM
+ENTRY(cpu_arm926_do_suspend)
+        stmfd   sp!, {r4 - r7, lr}
+        mrc     p15, 0, r4, c13, c0, 0  @ PID
+        mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
+        mrc     p15, 0, r6, c2, c0, 0   @ TTB address
+        mrc     p15, 0, r7, c1, c0, 0   @ Control register
+        stmia   r0, {r4 - r7}
+        ldmfd   sp!, {r4 - r7, pc}
+ENDPROC(cpu_arm926_do_suspend)
+
+ENTRY(cpu_arm926_do_resume)
+        mov     ip, #0
+        mcr     p15, 0, ip, c8, c7, 0   @ invalidate I+D TLBs
+        mcr     p15, 0, ip, c7, c7, 0   @ invalidate I+D caches
+        ldmia   r0, {r4 - r7}
+        mcr     p15, 0, r4, c13, c0, 0  @ PID
+        mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
+        mcr     p15, 0, r6, c2, c0, 0   @ TTB address
+        mov     r0, r7                  @ control register
+        mov     r2, r6, lsr #14         @ get TTB0 base
+        mov     r2, r2, lsl #14
+        ldr     r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
+                     PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
+        b       cpu_resume_mmu
+ENDPROC(cpu_arm926_do_resume)
+#else
+#define cpu_arm926_do_suspend   0
+#define cpu_arm926_do_resume    0
+#endif
+
         __CPUINIT
 
         .type   __arm926_setup, #function
@@ -456,6 +490,9 @@ arm926_processor_functions:
         .word   cpu_arm926_dcache_clean_area
         .word   cpu_arm926_switch_mm
         .word   cpu_arm926_set_pte_ext
+        .word   cpu_arm926_suspend_size
+        .word   cpu_arm926_do_suspend
+        .word   cpu_arm926_do_resume
         .size   arm926_processor_functions, . - arm926_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 7b11cdb9935f..26aea3f71c26 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -363,6 +363,9 @@ ENTRY(arm940_processor_functions)
         .word   cpu_arm940_dcache_clean_area
         .word   cpu_arm940_switch_mm
         .word   0               @ cpu_*_set_pte
+        .word   0
+        .word   0
+        .word   0
         .size   arm940_processor_functions, . - arm940_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 1a5bbf080342..8063345406fe 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -419,6 +419,9 @@ ENTRY(arm946_processor_functions)
         .word   cpu_arm946_dcache_clean_area
         .word   cpu_arm946_switch_mm
         .word   0               @ cpu_*_set_pte
+        .word   0
+        .word   0
+        .word   0
         .size   arm946_processor_functions, . - arm946_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index db67e3134d7a..7b7ebd4d096d 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -70,6 +70,9 @@ ENTRY(arm9tdmi_processor_functions)
                 .word   cpu_arm9tdmi_dcache_clean_area
                 .word   cpu_arm9tdmi_switch_mm
                 .word   0               @ cpu_*_set_pte
+                .word   0
+                .word   0
+                .word   0
                 .size   arm9tdmi_processor_functions, . - arm9tdmi_processor_functions
 
                 .section ".rodata"
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 7c9ad621f0e6..fc2a4ae15cf4 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -195,6 +195,9 @@ fa526_processor_functions:
         .word   cpu_fa526_dcache_clean_area
         .word   cpu_fa526_switch_mm
         .word   cpu_fa526_set_pte_ext
+        .word   0
+        .word   0
+        .word   0
         .size   fa526_processor_functions, . - fa526_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index b4597edbff97..d3883eed7a4a 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -554,6 +554,9 @@ feroceon_processor_functions:
         .word   cpu_feroceon_dcache_clean_area
         .word   cpu_feroceon_switch_mm
         .word   cpu_feroceon_set_pte_ext
+        .word   0
+        .word   0
+        .word   0
         .size   feroceon_processor_functions, . - feroceon_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 4458ee6aa713..9d4f2ae63370 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -388,6 +388,9 @@ mohawk_processor_functions:
         .word   cpu_mohawk_dcache_clean_area
         .word   cpu_mohawk_switch_mm
         .word   cpu_mohawk_set_pte_ext
+        .word   0
+        .word   0
+        .word   0
         .size   mohawk_processor_functions, . - mohawk_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 5aa8d59c2e85..46f09ed16b98 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -203,6 +203,9 @@ ENTRY(sa110_processor_functions)
         .word   cpu_sa110_dcache_clean_area
         .word   cpu_sa110_switch_mm
         .word   cpu_sa110_set_pte_ext
+        .word   0
+        .word   0
+        .word   0
         .size   sa110_processor_functions, . - sa110_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 2ac4e6f10713..74483d1977fe 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -169,6 +169,42 @@ ENTRY(cpu_sa1100_set_pte_ext)
 #endif
         mov     pc, lr
 
+.globl  cpu_sa1100_suspend_size
+.equ    cpu_sa1100_suspend_size, 4*4
+#ifdef CONFIG_PM
+ENTRY(cpu_sa1100_do_suspend)
+        stmfd   sp!, {r4 - r7, lr}
+        mrc     p15, 0, r4, c3, c0, 0           @ domain ID
+        mrc     p15, 0, r5, c2, c0, 0           @ translation table base addr
+        mrc     p15, 0, r6, c13, c0, 0          @ PID
+        mrc     p15, 0, r7, c1, c0, 0           @ control reg
+        stmia   r0, {r4 - r7}                   @ store cp regs
+        ldmfd   sp!, {r4 - r7, pc}
+ENDPROC(cpu_sa1100_do_suspend)
+
+ENTRY(cpu_sa1100_do_resume)
+        ldmia   r0, {r4 - r7}                   @ load cp regs
+        mov     r1, #0
+        mcr     p15, 0, r1, c8, c7, 0           @ flush I+D TLBs
+        mcr     p15, 0, r1, c7, c7, 0           @ flush I&D cache
+        mcr     p15, 0, r1, c9, c0, 0           @ invalidate RB
+        mcr     p15, 0, r1, c9, c0, 5           @ allow user space to use RB
+
+        mcr     p15, 0, r4, c3, c0, 0           @ domain ID
+        mcr     p15, 0, r5, c2, c0, 0           @ translation table base addr
+        mcr     p15, 0, r6, c13, c0, 0          @ PID
+        mov     r0, r7                          @ control register
+        mov     r2, r5, lsr #14                 @ get TTB0 base
+        mov     r2, r2, lsl #14
+        ldr     r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
+                     PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
+        b       cpu_resume_mmu
+ENDPROC(cpu_sa1100_do_resume)
+#else
+#define cpu_sa1100_do_suspend   0
+#define cpu_sa1100_do_resume    0
+#endif
+
         __CPUINIT
 
         .type   __sa1100_setup, #function
@@ -218,6 +254,9 @@ ENTRY(sa1100_processor_functions)
         .word   cpu_sa1100_dcache_clean_area
         .word   cpu_sa1100_switch_mm
         .word   cpu_sa1100_set_pte_ext
+        .word   cpu_sa1100_suspend_size
+        .word   cpu_sa1100_do_suspend
+        .word   cpu_sa1100_do_resume
         .size   sa1100_processor_functions, . - sa1100_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 59a7e1ffe7bc..832b6bdc192c 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -121,6 +121,53 @@ ENTRY(cpu_v6_set_pte_ext)
 #endif
         mov     pc, lr
 
+/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
+.globl  cpu_v6_suspend_size
+.equ    cpu_v6_suspend_size, 4 * 8
+#ifdef CONFIG_PM
+ENTRY(cpu_v6_do_suspend)
+        stmfd   sp!, {r4 - r11, lr}
+        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+        mrc     p15, 0, r5, c13, c0, 1  @ Context ID
+        mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
+        mrc     p15, 0, r7, c2, c0, 0   @ Translation table base 0
+        mrc     p15, 0, r8, c2, c0, 1   @ Translation table base 1
+        mrc     p15, 0, r9, c1, c0, 1   @ auxillary control register
+        mrc     p15, 0, r10, c1, c0, 2  @ co-processor access control
+        mrc     p15, 0, r11, c1, c0, 0  @ control register
+        stmia   r0, {r4 - r11}
+        ldmfd   sp!, {r4- r11, pc}
+ENDPROC(cpu_v6_do_suspend)
+
+ENTRY(cpu_v6_do_resume)
+        mov     ip, #0
+        mcr     p15, 0, ip, c7, c14, 0  @ clean+invalidate D cache
+        mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
+        mcr     p15, 0, ip, c7, c15, 0  @ clean+invalidate cache
+        mcr     p15, 0, ip, c7, c10, 4  @ drain write buffer
+        ldmia   r0, {r4 - r11}
+        mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+        mcr     p15, 0, r5, c13, c0, 1  @ Context ID
+        mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
+        mcr     p15, 0, r7, c2, c0, 0   @ Translation table base 0
+        mcr     p15, 0, r8, c2, c0, 1   @ Translation table base 1
+        mcr     p15, 0, r9, c1, c0, 1   @ auxillary control register
+        mcr     p15, 0, r10, c1, c0, 2  @ co-processor access control
+        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
+        mcr     p15, 0, ip, c7, c5, 4   @ ISB
+        mov     r0, r11                 @ control register
+        mov     r2, r7, lsr #14         @ get TTB0 base
+        mov     r2, r2, lsl #14
+        ldr     r3, cpu_resume_l1_flags
+        b       cpu_resume_mmu
+ENDPROC(cpu_v6_do_resume)
+cpu_resume_l1_flags:
+        ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
+        ALT_UP(.long  PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
+#else
+#define cpu_v6_do_suspend 0
+#define cpu_v6_do_resume 0
+#endif
 
 
         .type   cpu_v6_name, #object
@@ -206,6 +253,9 @@ ENTRY(v6_processor_functions)
         .word   cpu_v6_dcache_clean_area
         .word   cpu_v6_switch_mm
         .word   cpu_v6_set_pte_ext
+        .word   cpu_v6_suspend_size
+        .word   cpu_v6_do_suspend
+        .word   cpu_v6_do_resume
         .size   v6_processor_functions, . - v6_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 0c1172b56b4e..a5187ddfb267 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -171,6 +171,87 @@ cpu_v7_name:
         .ascii  "ARMv7 Processor"
         .align
 
+        /*
+         * Memory region attributes with SCTLR.TRE=1
+         *
+         *   n = TEX[0],C,B
+         *   TR = PRRR[2n+1:2n]         - memory type
+         *   IR = NMRR[2n+1:2n]         - inner cacheable property
+         *   OR = NMRR[2n+17:2n+16]     - outer cacheable property
+         *
+         *                      n       TR      IR      OR
+         *   UNCACHED           000     00
+         *   BUFFERABLE         001     10      00      00
+         *   WRITETHROUGH       010     10      10      10
+         *   WRITEBACK          011     10      11      11
+         *   reserved           110
+         *   WRITEALLOC         111     10      01      01
+         *   DEV_SHARED         100     01
+         *   DEV_NONSHARED      100     01
+         *   DEV_WC             001     10
+         *   DEV_CACHED         011     10
+         *
+         * Other attributes:
+         *
+         *   DS0 = PRRR[16] = 0         - device shareable property
+         *   DS1 = PRRR[17] = 1         - device shareable property
+         *   NS0 = PRRR[18] = 0         - normal shareable property
+         *   NS1 = PRRR[19] = 1         - normal shareable property
+         *   NOS = PRRR[24+n] = 1       - not outer shareable
+         */
+.equ    PRRR,   0xff0a81a8
+.equ    NMRR,   0x40e040e0
+
+/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
+.globl  cpu_v7_suspend_size
+.equ    cpu_v7_suspend_size, 4 * 8
+#ifdef CONFIG_PM
+ENTRY(cpu_v7_do_suspend)
+        stmfd   sp!, {r4 - r11, lr}
+        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+        mrc     p15, 0, r5, c13, c0, 1  @ Context ID
+        mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
+        mrc     p15, 0, r7, c2, c0, 0   @ TTB 0
+        mrc     p15, 0, r8, c2, c0, 1   @ TTB 1
+        mrc     p15, 0, r9, c1, c0, 0   @ Control register
+        mrc     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
+        mrc     p15, 0, r11, c1, c0, 2  @ Co-processor access control
+        stmia   r0, {r4 - r11}
+        ldmfd   sp!, {r4 - r11, pc}
+ENDPROC(cpu_v7_do_suspend)
+
+ENTRY(cpu_v7_do_resume)
+        mov     ip, #0
+        mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
+        mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
+        ldmia   r0, {r4 - r11}
+        mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+        mcr     p15, 0, r5, c13, c0, 1  @ Context ID
+        mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
+        mcr     p15, 0, r7, c2, c0, 0   @ TTB 0
+        mcr     p15, 0, r8, c2, c0, 1   @ TTB 1
+        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
+        mcr     p15, 0, r10, c1, c0, 1  @ Auxillary control register
+        mcr     p15, 0, r11, c1, c0, 2  @ Co-processor access control
+        ldr     r4, =PRRR               @ PRRR
+        ldr     r5, =NMRR               @ NMRR
+        mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
+        mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
+        isb
+        mov     r0, r9                  @ control register
+        mov     r2, r7, lsr #14         @ get TTB0 base
+        mov     r2, r2, lsl #14
+        ldr     r3, cpu_resume_l1_flags
+        b       cpu_resume_mmu
+ENDPROC(cpu_v7_do_resume)
+cpu_resume_l1_flags:
+        ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
+        ALT_UP(.long  PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
+#else
+#define cpu_v7_do_suspend       0
+#define cpu_v7_do_resume        0
+#endif
+
         __CPUINIT
 
 /*
@@ -276,36 +357,8 @@ __v7_setup:
         ALT_SMP(orr     r4, r4, #TTB_FLAGS_SMP)
         ALT_UP(orr      r4, r4, #TTB_FLAGS_UP)
         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
-        /*
-         * Memory region attributes with SCTLR.TRE=1
-         *
-         *   n = TEX[0],C,B
-         *   TR = PRRR[2n+1:2n]         - memory type
-         *   IR = NMRR[2n+1:2n]         - inner cacheable property
-         *   OR = NMRR[2n+17:2n+16]     - outer cacheable property
-         *
-         *                      n       TR      IR      OR
-         *   UNCACHED           000     00
-         *   BUFFERABLE         001     10      00      00
-         *   WRITETHROUGH       010     10      10      10
-         *   WRITEBACK          011     10      11      11
-         *   reserved           110
-         *   WRITEALLOC         111     10      01      01
-         *   DEV_SHARED         100     01
-         *   DEV_NONSHARED      100     01
-         *   DEV_WC             001     10
-         *   DEV_CACHED         011     10
-         *
-         * Other attributes:
-         *
-         *   DS0 = PRRR[16] = 0         - device shareable property
-         *   DS1 = PRRR[17] = 1         - device shareable property
-         *   NS0 = PRRR[18] = 0         - normal shareable property
-         *   NS1 = PRRR[19] = 1         - normal shareable property
-         *   NOS = PRRR[24+n] = 1       - not outer shareable
-         */
-        ldr     r5, =0xff0a81a8                 @ PRRR
-        ldr     r6, =0x40e040e0                 @ NMRR
+        ldr     r5, =PRRR                       @ PRRR
+        ldr     r6, =NMRR                       @ NMRR
         mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 #endif
@@ -351,6 +404,9 @@ ENTRY(v7_processor_functions)
         .word   cpu_v7_dcache_clean_area
         .word   cpu_v7_switch_mm
         .word   cpu_v7_set_pte_ext
+        .word   0
+        .word   0
+        .word   0
         .size   v7_processor_functions, . - v7_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index ec26355cb7c2..63d8b2044e84 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -413,9 +413,52 @@ ENTRY(cpu_xsc3_set_pte_ext)
         mov     pc, lr
 
         .ltorg
-
         .align
 
+.globl  cpu_xsc3_suspend_size
+.equ    cpu_xsc3_suspend_size, 4 * 8
+#ifdef CONFIG_PM
+ENTRY(cpu_xsc3_do_suspend)
+        stmfd   sp!, {r4 - r10, lr}
+        mrc     p14, 0, r4, c6, c0, 0   @ clock configuration, for turbo mode
+        mrc     p15, 0, r5, c15, c1, 0  @ CP access reg
+        mrc     p15, 0, r6, c13, c0, 0  @ PID
+        mrc     p15, 0, r7, c3, c0, 0   @ domain ID
+        mrc     p15, 0, r8, c2, c0, 0   @ translation table base addr
+        mrc     p15, 0, r9, c1, c0, 1   @ auxiliary control reg
+        mrc     p15, 0, r10, c1, c0, 0  @ control reg
+        bic     r4, r4, #2              @ clear frequency change bit
+        stmia   r0, {r1, r4 - r10}      @ store v:p offset + cp regs
+        ldmia   sp!, {r4 - r10, pc}
+ENDPROC(cpu_xsc3_do_suspend)
+
+ENTRY(cpu_xsc3_do_resume)
+        ldmia   r0, {r1, r4 - r10}      @ load v:p offset + cp regs
+        mov     ip, #0
+        mcr     p15, 0, ip, c7, c7, 0   @ invalidate I & D caches, BTB
+        mcr     p15, 0, ip, c7, c10, 4  @ drain write (&fill) buffer
+        mcr     p15, 0, ip, c7, c5, 4   @ flush prefetch buffer
+        mcr     p15, 0, ip, c8, c7, 0   @ invalidate I & D TLBs
+        mcr     p14, 0, r4, c6, c0, 0   @ clock configuration, turbo mode.
+        mcr     p15, 0, r5, c15, c1, 0  @ CP access reg
+        mcr     p15, 0, r6, c13, c0, 0  @ PID
+        mcr     p15, 0, r7, c3, c0, 0   @ domain ID
+        mcr     p15, 0, r8, c2, c0, 0   @ translation table base addr
+        mcr     p15, 0, r9, c1, c0, 1   @ auxiliary control reg
+
+        @ temporarily map resume_turn_on_mmu into the page table,
+        @ otherwise prefetch abort occurs after MMU is turned on
+        mov     r0, r10                 @ control register
+        mov     r2, r8, lsr #14         @ get TTB0 base
+        mov     r2, r2, lsl #14
+        ldr     r3, =0x542e             @ section flags
+        b       cpu_resume_mmu
+ENDPROC(cpu_xsc3_do_resume)
+#else
+#define cpu_xsc3_do_suspend     0
+#define cpu_xsc3_do_resume      0
+#endif
+
         __CPUINIT
 
         .type   __xsc3_setup, #function
@@ -476,6 +519,9 @@ ENTRY(xsc3_processor_functions)
         .word   cpu_xsc3_dcache_clean_area
         .word   cpu_xsc3_switch_mm
         .word   cpu_xsc3_set_pte_ext
+        .word   cpu_xsc3_suspend_size
+        .word   cpu_xsc3_do_suspend
+        .word   cpu_xsc3_do_resume
         .size   xsc3_processor_functions, . - xsc3_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 5a37c5e45c41..086038cd86ab 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -513,11 +513,49 @@ ENTRY(cpu_xscale_set_pte_ext)
         xscale_set_pte_ext_epilogue
         mov     pc, lr
 
-
         .ltorg
-
         .align
 
+.globl  cpu_xscale_suspend_size
+.equ    cpu_xscale_suspend_size, 4 * 7
+#ifdef CONFIG_PM
+ENTRY(cpu_xscale_do_suspend)
+        stmfd   sp!, {r4 - r10, lr}
+        mrc     p14, 0, r4, c6, c0, 0   @ clock configuration, for turbo mode
+        mrc     p15, 0, r5, c15, c1, 0  @ CP access reg
+        mrc     p15, 0, r6, c13, c0, 0  @ PID
+        mrc     p15, 0, r7, c3, c0, 0   @ domain ID
+        mrc     p15, 0, r8, c2, c0, 0   @ translation table base addr
+        mrc     p15, 0, r9, c1, c1, 0   @ auxiliary control reg
+        mrc     p15, 0, r10, c1, c0, 0  @ control reg
+        bic     r4, r4, #2              @ clear frequency change bit
+        stmia   r0, {r4 - r10}          @ store cp regs
+        ldmfd   sp!, {r4 - r10, pc}
+ENDPROC(cpu_xscale_do_suspend)
+
+ENTRY(cpu_xscale_do_resume)
+        ldmia   r0, {r4 - r10}          @ load cp regs
+        mov     ip, #0
+        mcr     p15, 0, ip, c8, c7, 0   @ invalidate I & D TLBs
+        mcr     p15, 0, ip, c7, c7, 0   @ invalidate I & D caches, BTB
+        mcr     p14, 0, r4, c6, c0, 0   @ clock configuration, turbo mode.
+        mcr     p15, 0, r5, c15, c1, 0  @ CP access reg
+        mcr     p15, 0, r6, c13, c0, 0  @ PID
+        mcr     p15, 0, r7, c3, c0, 0   @ domain ID
+        mcr     p15, 0, r8, c2, c0, 0   @ translation table base addr
+        mcr     p15, 0, r9, c1, c1, 0   @ auxiliary control reg
+        mov     r0, r10                 @ control register
+        mov     r2, r8, lsr #14         @ get TTB0 base
+        mov     r2, r2, lsl #14
+        ldr     r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
+                     PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
+        b       cpu_resume_mmu
+ENDPROC(cpu_xscale_do_resume)
+#else
+#define cpu_xscale_do_suspend   0
+#define cpu_xscale_do_resume    0
+#endif
+
         __CPUINIT
 
         .type   __xscale_setup, #function
@@ -565,6 +603,9 @@ ENTRY(xscale_processor_functions)
         .word   cpu_xscale_dcache_clean_area
         .word   cpu_xscale_switch_mm
         .word   cpu_xscale_set_pte_ext
+        .word   cpu_xscale_suspend_size
+        .word   cpu_xscale_do_suspend
+        .word   cpu_xscale_do_resume
         .size   xscale_processor_functions, . - xscale_processor_functions
 
         .section ".rodata"