Merge branch 'master'

7 files changed, 63 insertions, 62 deletions

diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 5c4055b62d97..54e3c5bb5186 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -10,7 +10,7 @@
 #include <linux/config.h>
 #include <linux/linkage.h>
 #include <linux/init.h>
-#include <asm/hardware.h>
+#include <asm/memory.h>
 #include <asm/page.h>
 #include "proc-macros.S"
 
@@ -46,6 +46,11 @@
  */
 #define CACHE_DLIMIT    (CACHE_DSIZE * 4)
 
+        .data
+flush_base:
+        .long   FLUSH_BASE
+        .text
+
 /*
  *      flush_user_cache_all()
  *
@@ -63,11 +68,21 @@ ENTRY(v4wb_flush_kern_cache_all)
         mov     ip, #0
         mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
 __flush_whole_cache:
-        mov     r0, #FLUSH_BASE
-        add     r1, r0, #CACHE_DSIZE
-1:      ldr     r2, [r0], #32
-        cmp     r0, r1
+        ldr     r3, =flush_base
+        ldr     r1, [r3, #0]
+        eor     r1, r1, #CACHE_DSIZE
+        str     r1, [r3, #0]
+        add     r2, r1, #CACHE_DSIZE
+1:      ldr     r3, [r1], #32
+        cmp     r1, r2
+        blo     1b
+#ifdef FLUSH_BASE_MINICACHE
+        add     r2, r2, #FLUSH_BASE_MINICACHE - FLUSH_BASE
+        sub     r1, r2, #512                    @ only 512 bytes
+1:      ldr     r3, [r1], #32
+        cmp     r1, r2
         blo     1b
+#endif
         mcr     p15, 0, ip, c7, c10, 4          @ drain write buffer
         mov     pc, lr
 
@@ -82,6 +97,7 @@ __flush_whole_cache:
  *      - flags - vma_area_struct flags describing address space
  */
 ENTRY(v4wb_flush_user_cache_range)
+        mov     ip, #0
         sub     r3, r1, r0                      @ calculate total size
         tst     r2, #VM_EXEC                    @ executable region?
         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c
index 8a1bfcd50087..50e6b6bfb2e2 100644
--- a/arch/arm/mm/consistent.c
+++ b/arch/arm/mm/consistent.c
@@ -18,6 +18,7 @@
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 
+#include <asm/memory.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
 #include <asm/sizes.h>
@@ -272,6 +273,17 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
 void *
 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp)
 {
+        if (arch_is_coherent()) {
+                void *virt;
+
+                virt = kmalloc(size, gfp);
+                if (!virt)
+                        return NULL;
+                *handle =  virt_to_dma(dev, virt);
+
+                return virt;
+        }
+
         return __dma_alloc(dev, size, handle, gfp,
                            pgprot_noncached(pgprot_kernel));
 }
@@ -350,6 +362,11 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr
 
         WARN_ON(irqs_disabled());
 
+        if (arch_is_coherent()) {
+                kfree(cpu_addr);
+                return;
+        }
+
         size = PAGE_ALIGN(size);
 
         spin_lock_irqsave(&consistent_lock, flags);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 88279124317a..9ea1f87a7079 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -20,6 +20,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/setup.h>
+#include <asm/sizes.h>
 #include <asm/tlb.h>
 
 #include <asm/mach/arch.h>
@@ -455,14 +456,14 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 #ifdef FLUSH_BASE
         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
         map.virtual = FLUSH_BASE;
-        map.length = PGDIR_SIZE;
+        map.length = SZ_1M;
         map.type = MT_CACHECLEAN;
         create_mapping(&map);
 #endif
 #ifdef FLUSH_BASE_MINICACHE
-        map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + PGDIR_SIZE);
+        map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
         map.virtual = FLUSH_BASE_MINICACHE;
-        map.length = PGDIR_SIZE;
+        map.length = SZ_1M;
         map.type = MT_MINICLEAN;
         create_mapping(&map);
 #endif
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index 5e5d05bcad50..f14b2d0f3690 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -389,6 +389,17 @@ void __init build_mem_type_table(void)
         kern_pgprot = user_pgprot = cp->pte;
 
         /*
+         * Enable CPU-specific coherency if supported.
+         * (Only available on XSC3 at the moment.)
+         */
+        if (arch_is_coherent()) {
+                if (cpu_is_xsc3()) {
+                        mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+                        mem_types[MT_MEMORY].prot_pte |= L_PTE_COHERENT;
+                }
+        }
+
+        /*
          * ARMv6 and above have extended page tables.
          */
         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index c916a6cae404..a2dd5ae1077d 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -26,22 +26,7 @@
  * the cache line size of the I and D cache
  */
 #define DCACHELINESIZE  32
-#define FLUSH_OFFSET    32768
 
-        .macro flush_110_dcache rd, ra, re
-        ldr     \rd, =flush_base
-        ldr     \ra, [\rd]
-        eor     \ra, \ra, #FLUSH_OFFSET
-        str     \ra, [\rd]
-        add     \re, \ra, #16384                @ only necessary for 16k
-1001:   ldr     \rd, [\ra], #DCACHELINESIZE
-        teq     \re, \ra
-        bne     1001b
-        .endm
-
-        .data
-flush_base:
-        .long   FLUSH_BASE
         .text
 
 /*
@@ -145,13 +130,11 @@ ENTRY(cpu_sa110_dcache_clean_area)
  */
         .align  5
 ENTRY(cpu_sa110_switch_mm)
-        flush_110_dcache        r3, ip, r1
-        mov     r1, #0
-        mcr     p15, 0, r1, c7, c5, 0           @ invalidate I cache
-        mcr     p15, 0, r1, c7, c10, 4          @ drain WB
+        str     lr, [sp, #-4]!
+        bl      v4wb_flush_kern_cache_all       @ clears IP
         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
-        mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
-        mov     pc, lr
+        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
+        ldr     pc, [sp], #4
 
 /*
  * cpu_sa110_set_pte(ptep, pte)
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 41f21f2dd8ff..777ad99c1439 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -30,30 +30,6 @@
  * the cache line size of the I and D cache
  */
 #define DCACHELINESIZE  32
-#define FLUSH_OFFSET    32768
-
-        .macro flush_1100_dcache rd, ra, re
-        ldr     \rd, =flush_base
-        ldr     \ra, [\rd]
-        eor     \ra, \ra, #FLUSH_OFFSET
-        str     \ra, [\rd]
-        add     \re, \ra, #8192                 @ only necessary for 8k
-1001:   ldr     \rd, [\ra], #DCACHELINESIZE
-        teq     \re, \ra
-        bne     1001b
-#ifdef FLUSH_BASE_MINICACHE
-        add     \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE
-        add     \re, \ra, #512                  @ only 512 bytes
-1002:   ldr     \rd, [\ra], #DCACHELINESIZE
-        teq     \re, \ra
-        bne     1002b
-#endif
-        .endm
-
-        .data
-flush_base:
-        .long   FLUSH_BASE
-        .text
 
         __INIT
 
@@ -79,9 +55,8 @@ ENTRY(cpu_sa1100_proc_fin)
         stmfd   sp!, {lr}
         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
         msr     cpsr_c, ip
-        flush_1100_dcache r0, r1, r2            @ clean caches
-        mov     r0, #0
-        mcr     p15, 0, r0, c15, c2, 2          @ Disable clock switching
+        bl      v4wb_flush_kern_cache_all
+        mcr     p15, 0, ip, c15, c2, 2          @ Disable clock switching
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
@@ -167,14 +142,12 @@ ENTRY(cpu_sa1100_dcache_clean_area)
  */
         .align  5
 ENTRY(cpu_sa1100_switch_mm)
-        flush_1100_dcache r3, ip, r1
-        mov     ip, #0
-        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
+        str     lr, [sp, #-4]!
+        bl      v4wb_flush_kern_cache_all       @ clears IP
         mcr     p15, 0, ip, c9, c0, 0           @ invalidate RB
-        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
-        mov     pc, lr
+        ldr     pc, [sp], #4
 
 /*
  * cpu_sa1100_set_pte(ptep, pte)
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index b9dfce57c272..80873b36c3f7 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -371,7 +371,7 @@ ENTRY(cpu_xsc3_switch_mm)
 ENTRY(cpu_xsc3_set_pte)
         str     r1, [r0], #-2048                @ linux version
 
-        bic     r2, r1, #0xff0
+        bic     r2, r1, #0xdf0                  @ Keep C, B, coherency bits
         orr     r2, r2, #PTE_TYPE_EXT           @ extended page
 
         eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY