Merge tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC specific changes from Arnd Bergmann:
 "Lots of changes specific to one of the SoC families.  Some that stick
  out are:

   - mach-qcom gains new features, most importantly SMP support for the
     newer chips (Stephen Boyd, Rohit Vaswani)
   - mvebu gains support for three new SoCs: Armada 375, 380 and 385
     (Thomas Petazzoni and Free-electrons team)
   - SMP support for Rockchips (Heiko Stübner)
   - Lots of i.MX changes (Shawn Guo)
   - Added support for BCM5301x SoC (Hauke Mehrtens)
   - Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn
     and Sebastian Hesselbarth doing the final part of a long journey)
   - Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd
     Bergmann)"

* tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits)
  ARM: sunxi: Select HAVE_ARM_ARCH_TIMER
  ARM: cache-tauros2: remove ARMv6 code
  ARM: mvebu: don't select CONFIG_NEON
  ARM: davinci: fix DT booting with default defconfig
  ARM: configs: bcm_defconfig: enable bcm590xx regulator support
  ARM: davinci: remove tnetv107x support
  MAINTAINERS: Update ARM STi maintainers
  ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE
  ARM: bcm21664: Add board support.
  ARM: sunxi: Add the new watchog compatibles to the reboot code
  ARM: enable ARM_HAS_SG_CHAIN for multiplatform
  ARM: davinci: remove da8xx_omapl_defconfig
  ARM: davinci: da8xx: fix multiple watchdog device registration
  ARM: davinci: add da8xx specific configs to davinci_all_defconfig
  ARM: davinci: enable da8xx build concurrently with older devices
  ARM: BCM5301X: workaround suppress fault
  ARM: BCM5301X: add early debugging support
  ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU
  ARM: mach-bcm: Remove GENERIC_TIME
  ARM: shmobile: APMU: Fix warnings due to improper printk formats
  ...

3 files changed, 46 insertions, 30 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 241622e2fea3..f5ad9ee70426 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -854,7 +854,7 @@ config OUTER_CACHE_SYNC
 
 config CACHE_FEROCEON_L2
         bool "Enable the Feroceon L2 cache controller"
-        depends on ARCH_KIRKWOOD || ARCH_MV78XX0
+        depends on ARCH_KIRKWOOD || ARCH_MV78XX0 || ARCH_MVEBU
         default y
         select OUTER_CACHE
         help
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index aae891820f8f..dc814a548056 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -13,10 +13,15 @@
  */
 
 #include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/highmem.h>
+#include <linux/io.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
-#include <plat/cache-feroceon-l2.h>
+#include <asm/hardware/cache-feroceon-l2.h>
+
+#define L2_WRITETHROUGH_KIRKWOOD        BIT(4)
 
 /*
  * Low-level cache maintenance operations.
@@ -352,3 +357,41 @@ void __init feroceon_l2_init(int __l2_wt_override)
         printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
                          l2_wt_override ? ", in WT override mode" : "");
 }
+#ifdef CONFIG_OF
+static const struct of_device_id feroceon_ids[] __initconst = {
+        { .compatible = "marvell,kirkwood-cache"},
+        { .compatible = "marvell,feroceon-cache"},
+        {}
+};
+
+int __init feroceon_of_init(void)
+{
+        struct device_node *node;
+        void __iomem *base;
+        bool l2_wt_override = false;
+        struct resource res;
+
+#if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
+        l2_wt_override = true;
+#endif
+
+        node = of_find_matching_node(NULL, feroceon_ids);
+        if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) {
+                if (of_address_to_resource(node, 0, &res))
+                        return -ENODEV;
+
+                base = ioremap(res.start, resource_size(&res));
+                if (!base)
+                        return -ENOMEM;
+
+                if (l2_wt_override)
+                        writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base);
+                else
+                        writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base);
+        }
+
+        feroceon_l2_init(l2_wt_override);
+
+        return 0;
+}
+#endif
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 1be0f4e5e6eb..b273739e6359 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -33,7 +33,7 @@
  * outer cache operations into the kernel image if the kernel has been
  * configured to support a pre-v7 CPU.
  */
-#if __LINUX_ARM_ARCH__ < 7
+#ifdef CONFIG_CPU_32v5
 /*
  * Low-level cache maintenance operations.
  */
@@ -229,33 +229,6 @@ static void __init tauros2_internal_init(unsigned int features)
         }
 #endif
 
-#ifdef CONFIG_CPU_32v6
-        /*
-         * Check whether this CPU lacks support for the v7 hierarchical
-         * cache ops.  (PJ4 is in its v6 personality mode if the MMFR3
-         * register indicates no support for the v7 hierarchical cache
-         * ops.)
-         */
-        if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
-                /*
-                 * When Tauros2 is used in an ARMv6 system, the L2
-                 * enable bit is in the ARMv6 ARM-mandated position
-                 * (bit [26] of the System Control Register).
-                 */
-                if (!(get_cr() & 0x04000000)) {
-                        printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
-                        adjust_cr(0x04000000, 0x04000000);
-                }
-
-                mode = "ARMv6";
-                outer_cache.inv_range = tauros2_inv_range;
-                outer_cache.clean_range = tauros2_clean_range;
-                outer_cache.flush_range = tauros2_flush_range;
-                outer_cache.disable = tauros2_disable;
-                outer_cache.resume = tauros2_resume;
-        }
-#endif
-
 #ifdef CONFIG_CPU_32v7
         /*
          * Check whether this CPU has support for the v7 hierarchical