diff options
author | David S. Miller <davem@davemloft.net> | 2011-06-21 01:29:08 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-06-21 01:29:08 -0400 |
commit | 9f6ec8d697c08963d83880ccd35c13c5ace716ea (patch) | |
tree | ad8d93cf6fcdd09b86ade09f5fcbbc66cdb1cca2 /arch/arm/mm | |
parent | 4aa3a715551c93eda32d79bd52042ce500bd5383 (diff) | |
parent | 56299378726d5f2ba8d3c8cbbd13cb280ba45e4f (diff) |
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts:
drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
drivers/net/wireless/rtlwifi/pci.c
net/netfilter/ipvs/ip_vs_core.c
Diffstat (limited to 'arch/arm/mm')
-rw-r--r-- | arch/arm/mm/context.c | 17 | ||||
-rw-r--r-- | arch/arm/mm/init.c | 12 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm7tdmi.S | 2 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm9tdmi.S | 2 | ||||
-rw-r--r-- | arch/arm/mm/proc-v7.S | 10 |
5 files changed, 26 insertions, 17 deletions
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 8bfae964b133..b0ee9ba3cfab 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c | |||
@@ -24,7 +24,9 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm); | |||
24 | 24 | ||
25 | /* | 25 | /* |
26 | * We fork()ed a process, and we need a new context for the child | 26 | * We fork()ed a process, and we need a new context for the child |
27 | * to run in. | 27 | * to run in. We reserve version 0 for initial tasks so we will |
28 | * always allocate an ASID. The ASID 0 is reserved for the TTBR | ||
29 | * register changing sequence. | ||
28 | */ | 30 | */ |
29 | void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) | 31 | void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) |
30 | { | 32 | { |
@@ -34,11 +36,8 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) | |||
34 | 36 | ||
35 | static void flush_context(void) | 37 | static void flush_context(void) |
36 | { | 38 | { |
37 | u32 ttb; | 39 | /* set the reserved ASID before flushing the TLB */ |
38 | /* Copy TTBR1 into TTBR0 */ | 40 | asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0)); |
39 | asm volatile("mrc p15, 0, %0, c2, c0, 1\n" | ||
40 | "mcr p15, 0, %0, c2, c0, 0" | ||
41 | : "=r" (ttb)); | ||
42 | isb(); | 41 | isb(); |
43 | local_flush_tlb_all(); | 42 | local_flush_tlb_all(); |
44 | if (icache_is_vivt_asid_tagged()) { | 43 | if (icache_is_vivt_asid_tagged()) { |
@@ -94,7 +93,7 @@ static void reset_context(void *info) | |||
94 | return; | 93 | return; |
95 | 94 | ||
96 | smp_rmb(); | 95 | smp_rmb(); |
97 | asid = cpu_last_asid + cpu; | 96 | asid = cpu_last_asid + cpu + 1; |
98 | 97 | ||
99 | flush_context(); | 98 | flush_context(); |
100 | set_mm_context(mm, asid); | 99 | set_mm_context(mm, asid); |
@@ -144,13 +143,13 @@ void __new_context(struct mm_struct *mm) | |||
144 | * to start a new version and flush the TLB. | 143 | * to start a new version and flush the TLB. |
145 | */ | 144 | */ |
146 | if (unlikely((asid & ~ASID_MASK) == 0)) { | 145 | if (unlikely((asid & ~ASID_MASK) == 0)) { |
147 | asid = cpu_last_asid + smp_processor_id(); | 146 | asid = cpu_last_asid + smp_processor_id() + 1; |
148 | flush_context(); | 147 | flush_context(); |
149 | #ifdef CONFIG_SMP | 148 | #ifdef CONFIG_SMP |
150 | smp_wmb(); | 149 | smp_wmb(); |
151 | smp_call_function(reset_context, NULL, 1); | 150 | smp_call_function(reset_context, NULL, 1); |
152 | #endif | 151 | #endif |
153 | cpu_last_asid += NR_CPUS - 1; | 152 | cpu_last_asid += NR_CPUS; |
154 | } | 153 | } |
155 | 154 | ||
156 | set_mm_context(mm, asid); | 155 | set_mm_context(mm, asid); |
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 2c2cce9cd8c8..c19571c40a21 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c | |||
@@ -331,6 +331,12 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc) | |||
331 | #endif | 331 | #endif |
332 | #ifdef CONFIG_BLK_DEV_INITRD | 332 | #ifdef CONFIG_BLK_DEV_INITRD |
333 | if (phys_initrd_size && | 333 | if (phys_initrd_size && |
334 | !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) { | ||
335 | pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n", | ||
336 | phys_initrd_start, phys_initrd_size); | ||
337 | phys_initrd_start = phys_initrd_size = 0; | ||
338 | } | ||
339 | if (phys_initrd_size && | ||
334 | memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) { | 340 | memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) { |
335 | pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n", | 341 | pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n", |
336 | phys_initrd_start, phys_initrd_size); | 342 | phys_initrd_start, phys_initrd_size); |
@@ -635,7 +641,8 @@ void __init mem_init(void) | |||
635 | " modules : 0x%08lx - 0x%08lx (%4ld MB)\n" | 641 | " modules : 0x%08lx - 0x%08lx (%4ld MB)\n" |
636 | " .init : 0x%p" " - 0x%p" " (%4d kB)\n" | 642 | " .init : 0x%p" " - 0x%p" " (%4d kB)\n" |
637 | " .text : 0x%p" " - 0x%p" " (%4d kB)\n" | 643 | " .text : 0x%p" " - 0x%p" " (%4d kB)\n" |
638 | " .data : 0x%p" " - 0x%p" " (%4d kB)\n", | 644 | " .data : 0x%p" " - 0x%p" " (%4d kB)\n" |
645 | " .bss : 0x%p" " - 0x%p" " (%4d kB)\n", | ||
639 | 646 | ||
640 | MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + | 647 | MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + |
641 | (PAGE_SIZE)), | 648 | (PAGE_SIZE)), |
@@ -657,7 +664,8 @@ void __init mem_init(void) | |||
657 | 664 | ||
658 | MLK_ROUNDUP(__init_begin, __init_end), | 665 | MLK_ROUNDUP(__init_begin, __init_end), |
659 | MLK_ROUNDUP(_text, _etext), | 666 | MLK_ROUNDUP(_text, _etext), |
660 | MLK_ROUNDUP(_sdata, _edata)); | 667 | MLK_ROUNDUP(_sdata, _edata), |
668 | MLK_ROUNDUP(__bss_start, __bss_stop)); | ||
661 | 669 | ||
662 | #undef MLK | 670 | #undef MLK |
663 | #undef MLM | 671 | #undef MLM |
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S index e4c165ca6696..537ffcb0646d 100644 --- a/arch/arm/mm/proc-arm7tdmi.S +++ b/arch/arm/mm/proc-arm7tdmi.S | |||
@@ -146,7 +146,7 @@ __arm7tdmi_proc_info: | |||
146 | .long 0 | 146 | .long 0 |
147 | .long 0 | 147 | .long 0 |
148 | .long v4_cache_fns | 148 | .long v4_cache_fns |
149 | .size __arm7tdmi_proc_info, . - __arm7dmi_proc_info | 149 | .size __arm7tdmi_proc_info, . - __arm7tdmi_proc_info |
150 | 150 | ||
151 | .type __triscenda7_proc_info, #object | 151 | .type __triscenda7_proc_info, #object |
152 | __triscenda7_proc_info: | 152 | __triscenda7_proc_info: |
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S index 7b7ebd4d096d..546b54da1005 100644 --- a/arch/arm/mm/proc-arm9tdmi.S +++ b/arch/arm/mm/proc-arm9tdmi.S | |||
@@ -116,7 +116,7 @@ __arm9tdmi_proc_info: | |||
116 | .long 0 | 116 | .long 0 |
117 | .long 0 | 117 | .long 0 |
118 | .long v4_cache_fns | 118 | .long v4_cache_fns |
119 | .size __arm9tdmi_proc_info, . - __arm9dmi_proc_info | 119 | .size __arm9tdmi_proc_info, . - __arm9tdmi_proc_info |
120 | 120 | ||
121 | .type __p2001_proc_info, #object | 121 | .type __p2001_proc_info, #object |
122 | __p2001_proc_info: | 122 | __p2001_proc_info: |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index b3b566ec83d3..3c3867850a30 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -108,16 +108,18 @@ ENTRY(cpu_v7_switch_mm) | |||
108 | #ifdef CONFIG_ARM_ERRATA_430973 | 108 | #ifdef CONFIG_ARM_ERRATA_430973 |
109 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB | 109 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
110 | #endif | 110 | #endif |
111 | mrc p15, 0, r2, c2, c0, 1 @ load TTB 1 | 111 | #ifdef CONFIG_ARM_ERRATA_754322 |
112 | mcr p15, 0, r2, c2, c0, 0 @ into TTB 0 | 112 | dsb |
113 | #endif | ||
114 | mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID | ||
115 | isb | ||
116 | 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | ||
113 | isb | 117 | isb |
114 | #ifdef CONFIG_ARM_ERRATA_754322 | 118 | #ifdef CONFIG_ARM_ERRATA_754322 |
115 | dsb | 119 | dsb |
116 | #endif | 120 | #endif |
117 | mcr p15, 0, r1, c13, c0, 1 @ set context ID | 121 | mcr p15, 0, r1, c13, c0, 1 @ set context ID |
118 | isb | 122 | isb |
119 | mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | ||
120 | isb | ||
121 | #endif | 123 | #endif |
122 | mov pc, lr | 124 | mov pc, lr |
123 | ENDPROC(cpu_v7_switch_mm) | 125 | ENDPROC(cpu_v7_switch_mm) |