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authorSaeed Bishara <saeed@marvell.com>2009-08-06 08:12:43 -0400
committerNicolas Pitre <nico@fluxnic.net>2009-11-27 15:43:06 -0500
commitedabd38e1a017e922e3e3b485ee3ddb4df433aa4 (patch)
treec79cef3e59f62014c12ff1203e84b0bac5610a55 /arch/arm/mm
parent8d27b2f7988b652dbabf79291a3e2550c06e1af5 (diff)
ARM: add base support for Marvell Dove SoC
The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/Kconfig2
-rw-r--r--arch/arm/mm/proc-v6.S33
2 files changed, 33 insertions, 2 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9264d814cd7a..1549863d7b54 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -388,7 +388,7 @@ config CPU_FEROCEON_OLD_ID
388 388
389# ARMv6 389# ARMv6
390config CPU_V6 390config CPU_V6
391 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 391 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE
392 select CPU_32v6 392 select CPU_32v6
393 select CPU_ABRT_EV6 393 select CPU_ABRT_EV6
394 select CPU_PABRT_V6 394 select CPU_PABRT_V6
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 70f75d2e3ead..5485c821101c 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -130,9 +130,16 @@ ENTRY(cpu_v6_set_pte_ext)
130 130
131 131
132 132
133 133 .type cpu_v6_name, #object
134cpu_v6_name: 134cpu_v6_name:
135 .asciz "ARMv6-compatible processor" 135 .asciz "ARMv6-compatible processor"
136 .size cpu_v6_name, . - cpu_v6_name
137
138 .type cpu_pj4_name, #object
139cpu_pj4_name:
140 .asciz "Marvell PJ4 processor"
141 .size cpu_pj4_name, . - cpu_pj4_name
142
136 .align 143 .align
137 144
138 __INIT 145 __INIT
@@ -241,3 +248,27 @@ __v6_proc_info:
241 .long v6_user_fns 248 .long v6_user_fns
242 .long v6_cache_fns 249 .long v6_cache_fns
243 .size __v6_proc_info, . - __v6_proc_info 250 .size __v6_proc_info, . - __v6_proc_info
251
252 .type __pj4_v6_proc_info, #object
253__pj4_v6_proc_info:
254 .long 0x560f5810
255 .long 0xff0ffff0
256 .long PMD_TYPE_SECT | \
257 PMD_SECT_BUFFERABLE | \
258 PMD_SECT_CACHEABLE | \
259 PMD_SECT_AP_WRITE | \
260 PMD_SECT_AP_READ
261 .long PMD_TYPE_SECT | \
262 PMD_SECT_XN | \
263 PMD_SECT_AP_WRITE | \
264 PMD_SECT_AP_READ
265 b __v6_setup
266 .long cpu_arch_name
267 .long cpu_elf_name
268 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
269 .long cpu_pj4_name
270 .long v6_processor_functions
271 .long v6wbi_tlb_fns
272 .long v6_user_fns
273 .long v6_cache_fns
274 .size __pj4_v6_proc_info, . - __pj4_v6_proc_info