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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2007-05-08 15:03:09 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-05-08 15:03:09 -0400
commit8678c1f04277daaa914abb107fb9fe71298d916d (patch)
treec4916538ff592210363909099aad866e1ba67985 /arch/arm/mm
parent08fdffd4cf4ddd4eb4b32e78f93f4ff53ccec78f (diff)
[ARM] Fix ASID version switch
Close a hole in the ASID version switch, particularly the following scenario: CPU0 MM PID CPU1 MM PID idle A pid(A) A idle(lazy tlb) * new asid version triggered by B * B pid(B) A pid(A) * MM A gets new asid version * A idle(lazy tlb) A pid(A) * CPU1 doesn't see the new ASID * The result is that CPU1 continues running with the hardware set for the original (stale) ASID value, but mm->context.id contains the new ASID value. The result is that the next MM fault on CPU1 updates the page table entries, but flush_tlb_page() fails due to wrong ASID. There is a related case with a threaded application is allocated a new ASID on one CPU while another of its threads is running on some different CPU. This scenario is not fixed by this commit. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/context.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 9da43a0fdcdf..930c04c4f53c 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -14,7 +14,8 @@
14#include <asm/mmu_context.h> 14#include <asm/mmu_context.h>
15#include <asm/tlbflush.h> 15#include <asm/tlbflush.h>
16 16
17unsigned int cpu_last_asid = { 1 << ASID_BITS }; 17static DEFINE_SPINLOCK(cpu_asid_lock);
18unsigned int cpu_last_asid = ASID_FIRST_VERSION;
18 19
19/* 20/*
20 * We fork()ed a process, and we need a new context for the child 21 * We fork()ed a process, and we need a new context for the child
@@ -31,15 +32,16 @@ void __new_context(struct mm_struct *mm)
31{ 32{
32 unsigned int asid; 33 unsigned int asid;
33 34
35 spin_lock(&cpu_asid_lock);
34 asid = ++cpu_last_asid; 36 asid = ++cpu_last_asid;
35 if (asid == 0) 37 if (asid == 0)
36 asid = cpu_last_asid = 1 << ASID_BITS; 38 asid = cpu_last_asid = ASID_FIRST_VERSION;
37 39
38 /* 40 /*
39 * If we've used up all our ASIDs, we need 41 * If we've used up all our ASIDs, we need
40 * to start a new version and flush the TLB. 42 * to start a new version and flush the TLB.
41 */ 43 */
42 if ((asid & ~ASID_MASK) == 0) { 44 if (unlikely((asid & ~ASID_MASK) == 0)) {
43 asid = ++cpu_last_asid; 45 asid = ++cpu_last_asid;
44 /* set the reserved ASID before flushing the TLB */ 46 /* set the reserved ASID before flushing the TLB */
45 asm("mcr p15, 0, %0, c13, c0, 1 @ set reserved context ID\n" 47 asm("mcr p15, 0, %0, c13, c0, 1 @ set reserved context ID\n"
@@ -48,6 +50,8 @@ void __new_context(struct mm_struct *mm)
48 isb(); 50 isb();
49 flush_tlb_all(); 51 flush_tlb_all();
50 } 52 }
53 spin_unlock(&cpu_asid_lock);
51 54
55 mm->cpu_vm_mask = cpumask_of_cpu(smp_processor_id());
52 mm->context.id = asid; 56 mm->context.id = asid;
53} 57}