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authorGeorge G. Davis <davis_g@com.rmk.(none)>2005-04-29 17:08:33 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-04-29 17:08:33 -0400
commit3a1e501511a1e2c665c566939047794dcf86466b (patch)
tree6803ebc7e2bfd6c9cdc6b4752d79da72cdd6088d /arch/arm/mm
parent458a83fa43e83505f9401783ce9ed41b5a8b5591 (diff)
[PATCH] ARM: 2655/1: ARM1136 SWP instruction abort handler fix
Patch from George G. Davis As noted in http://www.arm.com/linux/patch-2.6.9-arm1.gz, the "Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR." So the v6_early_abort handler does not report the correct rd/wr direction for the SWP instruction which may result in SEGVS or hangs. In order to work around this problem, this patch merely updates the fix contained in the ARM Ltd. patch to use the macroised abort handler fixups. Signed-off-by: George G. Davis Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/abort-ev6.S16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 38b2cbb89beb..8f76f3df7b4c 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -1,5 +1,6 @@
1#include <linux/linkage.h> 1#include <linux/linkage.h>
2#include <asm/assembler.h> 2#include <asm/assembler.h>
3#include "abort-macro.S"
3/* 4/*
4 * Function: v6_early_abort 5 * Function: v6_early_abort
5 * 6 *
@@ -13,11 +14,26 @@
13 * : sp = pointer to registers 14 * : sp = pointer to registers
14 * 15 *
15 * Purpose : obtain information about current aborted instruction. 16 * Purpose : obtain information about current aborted instruction.
17 * Note: we read user space. This means we might cause a data
18 * abort here if the I-TLB and D-TLB aren't seeing the same
19 * picture. Unfortunately, this does happen. We live with it.
16 */ 20 */
17 .align 5 21 .align 5
18ENTRY(v6_early_abort) 22ENTRY(v6_early_abort)
19 mrc p15, 0, r1, c5, c0, 0 @ get FSR 23 mrc p15, 0, r1, c5, c0, 0 @ get FSR
20 mrc p15, 0, r0, c6, c0, 0 @ get FAR 24 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25/*
26 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
27 * The test below covers all the write situations, including Java bytecodes
28 */
29 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
30 tst r3, #PSR_J_BIT @ Java?
31 movne pc, lr
32 do_thumb_abort
33 ldreq r3, [r2] @ read aborted ARM instruction
34 do_ldrd_abort
35 tst r3, #1 << 20 @ L = 0 -> write
36 orreq r1, r1, #1 << 11 @ yes.
21 mov pc, lr 37 mov pc, lr
22 38
23 39