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authorCatalin Marinas <catalin.marinas@arm.com>2011-05-26 06:22:44 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-05-26 07:14:32 -0400
commitd427958a46af24f75d0017c45eadd172273bbf33 (patch)
treee4279d383e7eaccdfe22420abe0a68a35bcc4c85 /arch/arm/mm
parenta248b13b21ae00b97638b4f435c8df3075808b5d (diff)
ARM: 6942/1: mm: make TTBR1 always point to swapper_pg_dir on ARMv6/7
This patch makes TTBR1 point to swapper_pg_dir so that global, kernel mappings can be used exclusively on v6 and v7 cores where they are needed. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/proc-v6.S4
-rw-r--r--arch/arm/mm/proc-v7.S4
2 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index ab17cc0d3fa7..1d2b8451bf25 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -213,7 +213,9 @@ __v6_setup:
213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
214 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 214 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
215 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 215 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
216 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 216 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
217 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
218 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
217#endif /* CONFIG_MMU */ 219#endif /* CONFIG_MMU */
218 adr r5, v6_crval 220 adr r5, v6_crval
219 ldmia r5, {r5, r6} 221 ldmia r5, {r5, r6}
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index babfba09c89f..3c3867850a30 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -368,7 +368,9 @@ __v7_setup:
368 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 368 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
369 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 369 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
370 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 370 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
371 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 371 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
372 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
373 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
372 ldr r5, =PRRR @ PRRR 374 ldr r5, =PRRR @ PRRR
373 ldr r6, =NMRR @ NMRR 375 ldr r6, =NMRR @ NMRR
374 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 376 mcr p15, 0, r5, c10, c2, 0 @ write PRRR