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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-20 20:56:23 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-20 20:56:23 -0500
commitf59dc2bb5a50b26ea751f9eac1c81e4cc7de5257 (patch)
tree4c1b3e0ea4bfbd8f9dd72ee95773f4be2dd087d2 /arch/arm/mm
parentf3dc1294c8a40d7eedd676b65f42f0b828fd3d8c (diff)
parente6ee4b2b57a8e0d8e551031173de080b338d3969 (diff)
Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King: "A number of smallish fixes scattered around the ARM code. Probably the most serious one is the one from Al addressing the missing locking in the swap emulation code." * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7607/1: realview: fix private peripheral memory base for EB rev. B boards ARM: 7606/1: cache: flush to LoUU instead of LoUIS on uniprocessor CPUs ARM: missing ->mmap_sem around find_vma() in swp_emulate.c ARM: 7605/1: vmlinux.lds: Move .notes section next to the rodata ARM: 7602/1: Pass real "__machine_arch_type" variable to setup_machine_tags() procedure ARM: 7600/1: include CONFIG_DEBUG_LL_INCLUDE rather than mach/debug-macro.S
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/cache-v7.S6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index cd956647c21a..7539ec275065 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -44,8 +44,10 @@ ENDPROC(v7_flush_icache_all)
44ENTRY(v7_flush_dcache_louis) 44ENTRY(v7_flush_dcache_louis)
45 dmb @ ensure ordering with previous memory accesses 45 dmb @ ensure ordering with previous memory accesses
46 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr 46 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
47 ands r3, r0, #0xe00000 @ extract LoUIS from clidr 47 ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
48 mov r3, r3, lsr #20 @ r3 = LoUIS * 2 48 ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
49 ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2
50 ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2
49 moveq pc, lr @ return if level == 0 51 moveq pc, lr @ return if level == 0
50 mov r10, #0 @ r10 (starting level) = 0 52 mov r10, #0 @ r10 (starting level) = 0
51 b flush_levels @ start flushing cache levels 53 b flush_levels @ start flushing cache levels