[ARM] nommu: confirms the CR_V bit in nommu mode

In nommu mode, the exception vector location depends on the platforms.
Some of the implementations may have some special exception control
forwarding method in their ROM/flash and for some of them has its own
re-mapping mechanism by the h/w.

This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which
turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default.
This feature depends on CP15 and does not supported by ARM740.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 12 insertions, 0 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 6c1bd424ea61..c0bfb8212b77 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -524,6 +524,18 @@ config CPU_BIG_ENDIAN
           port must properly enable any big-endian related features
           of your chipset/board/processor.
 
+config CPU_HIGH_VECTOR
+        depends !MMU && CPU_CP15 && !CPU_ARM740T
+        bool "Select the High exception vector"
+        default n
+        help
+          Say Y here to select high exception vector(0xFFFF0000~).
+          The exception vector can be vary depending on the platform
+          design in nommu mode. If your platform needs to select
+          high exception vector, say Y.
+          Otherwise or if you are unsure, say N, and the low exception
+          vector (0x00000000~) will be used.
+
 config CPU_ICACHE_DISABLE
         bool "Disable I-Cache (I-bit)"
         depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)