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authorCatalin Marinas <catalin.marinas@arm.com>2009-05-30 09:00:14 -0400
committerCatalin Marinas <catalin.marinas@arm.com>2009-05-30 09:00:14 -0400
commitfaa7bc51c11d5bbe440ac04710fd7a3208782000 (patch)
tree8aaa4e8e2fbb14b421988762fa90a3dbe6fa76e7 /arch/arm/mm/tlb-v7.S
parentda055eb52ec067d51dc08c7e86baf92dd5c01599 (diff)
Check whether the TLB operations need broadcasting on SMP systems
ARMv7 SMP hardware can handle the TLB maintenance operations broadcasting in hardware so that the software can avoid the costly IPIs. This patch adds the necessary checks (the MMFR3 CPUID register) to avoid the broadcasting if already supported by the hardware. (this patch is based on the work done by Tony Thompson @ ARM) Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm/tlb-v7.S')
-rw-r--r--arch/arm/mm/tlb-v7.S17
1 files changed, 11 insertions, 6 deletions
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index b637e7380ab7..a26a605b73bd 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -42,9 +42,11 @@ ENTRY(v7wbi_flush_user_tlb_range)
42 mov r1, r1, lsl #PAGE_SHIFT 42 mov r1, r1, lsl #PAGE_SHIFT
43 vma_vm_flags r2, r2 @ get vma->vm_flags 43 vma_vm_flags r2, r2 @ get vma->vm_flags
441: 441:
45 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 45#ifdef CONFIG_SMP
46 tst r2, #VM_EXEC @ Executable area ? 46 mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
47 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) 47#else
48 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
49#endif
48 add r0, r0, #PAGE_SZ 50 add r0, r0, #PAGE_SZ
49 cmp r0, r1 51 cmp r0, r1
50 blo 1b 52 blo 1b
@@ -69,8 +71,11 @@ ENTRY(v7wbi_flush_kern_tlb_range)
69 mov r0, r0, lsl #PAGE_SHIFT 71 mov r0, r0, lsl #PAGE_SHIFT
70 mov r1, r1, lsl #PAGE_SHIFT 72 mov r1, r1, lsl #PAGE_SHIFT
711: 731:
72 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 74#ifdef CONFIG_SMP
73 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 75 mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
76#else
77 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
78#endif
74 add r0, r0, #PAGE_SZ 79 add r0, r0, #PAGE_SZ
75 cmp r0, r1 80 cmp r0, r1
76 blo 1b 81 blo 1b
@@ -87,5 +92,5 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
87ENTRY(v7wbi_tlb_fns) 92ENTRY(v7wbi_tlb_fns)
88 .long v7wbi_flush_user_tlb_range 93 .long v7wbi_flush_user_tlb_range
89 .long v7wbi_flush_kern_tlb_range 94 .long v7wbi_flush_kern_tlb_range
90 .long v6wbi_tlb_flags 95 .long v7wbi_tlb_flags
91 .size v7wbi_tlb_fns, . - v7wbi_tlb_fns 96 .size v7wbi_tlb_fns, . - v7wbi_tlb_fns