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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-06-29 10:09:57 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-29 10:09:57 -0400
commit22b1908610dd7ff68471cd4fbd383dbdfe5e0ecd (patch)
tree696d910ef791433a6a6bbd30ae841a106ce78a88 /arch/arm/mm/proc-xscale.S
parent264edb35ce5c85749bfdd2942c74b786ea1cde41 (diff)
[ARM] nommu: provide a way for correct control register value selection
Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-xscale.S')
-rw-r--r--arch/arm/mm/proc-xscale.S16
1 files changed, 7 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 29bcc4dd6517..1ad0c880c80c 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -475,11 +475,12 @@ __xscale_setup:
475 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde 475 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
476 orr r0, r0, #1 << 13 @ Its undefined whether this 476 orr r0, r0, #1 << 13 @ Its undefined whether this
477 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 477 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
478
479 adr r5, xscale_crval
480 ldmia r5, {r5, r6}
478 mrc p15, 0, r0, c1, c0, 0 @ get control register 481 mrc p15, 0, r0, c1, c0, 0 @ get control register
479 ldr r5, xscale_cr1_clear
480 bic r0, r0, r5 482 bic r0, r0, r5
481 ldr r5, xscale_cr1_set 483 orr r0, r0, r6
482 orr r0, r0, r5
483 mov pc, lr 484 mov pc, lr
484 .size __xscale_setup, . - __xscale_setup 485 .size __xscale_setup, . - __xscale_setup
485 486
@@ -489,12 +490,9 @@ __xscale_setup:
489 * ..11 1.01 .... .101 490 * ..11 1.01 .... .101
490 * 491 *
491 */ 492 */
492 .type xscale_cr1_clear, #object 493 .type xscale_crval, #object
493 .type xscale_cr1_set, #object 494xscale_crval:
494xscale_cr1_clear: 495 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
495 .word 0x3b07
496xscale_cr1_set:
497 .word 0x3905
498 496
499 __INITDATA 497 __INITDATA
500 498