diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-11-26 11:24:19 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-02-15 10:22:23 -0500 |
commit | 702b94bff3c50542a6e4ab9a4f4cef093262fe65 (patch) | |
tree | 2ae468b08de2aeb0e65ab3830c40c7a84dbbdb5e /arch/arm/mm/proc-xscale.S | |
parent | a9c9147eb9b1dba0ce567a41897c7773b4d1b0bc (diff) |
ARM: dma-mapping: remove dmac_clean_range and dmac_inv_range
These are now unused, and so can be removed.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mm/proc-xscale.S')
-rw-r--r-- | arch/arm/mm/proc-xscale.S | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index a7999f94bf27..63037e2162f2 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S | |||
@@ -315,7 +315,7 @@ ENTRY(xscale_flush_kern_dcache_area) | |||
315 | * - start - virtual start address | 315 | * - start - virtual start address |
316 | * - end - virtual end address | 316 | * - end - virtual end address |
317 | */ | 317 | */ |
318 | ENTRY(xscale_dma_inv_range) | 318 | xscale_dma_inv_range: |
319 | tst r0, #CACHELINESIZE - 1 | 319 | tst r0, #CACHELINESIZE - 1 |
320 | bic r0, r0, #CACHELINESIZE - 1 | 320 | bic r0, r0, #CACHELINESIZE - 1 |
321 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 321 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -336,7 +336,7 @@ ENTRY(xscale_dma_inv_range) | |||
336 | * - start - virtual start address | 336 | * - start - virtual start address |
337 | * - end - virtual end address | 337 | * - end - virtual end address |
338 | */ | 338 | */ |
339 | ENTRY(xscale_dma_clean_range) | 339 | xscale_dma_clean_range: |
340 | bic r0, r0, #CACHELINESIZE - 1 | 340 | bic r0, r0, #CACHELINESIZE - 1 |
341 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 341 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
342 | add r0, r0, #CACHELINESIZE | 342 | add r0, r0, #CACHELINESIZE |
@@ -409,8 +409,6 @@ ENTRY(xscale_cache_fns) | |||
409 | .long xscale_flush_kern_dcache_area | 409 | .long xscale_flush_kern_dcache_area |
410 | .long xscale_dma_map_area | 410 | .long xscale_dma_map_area |
411 | .long xscale_dma_unmap_area | 411 | .long xscale_dma_unmap_area |
412 | .long xscale_dma_inv_range | ||
413 | .long xscale_dma_clean_range | ||
414 | .long xscale_dma_flush_range | 412 | .long xscale_dma_flush_range |
415 | 413 | ||
416 | /* | 414 | /* |
@@ -436,8 +434,6 @@ ENTRY(xscale_80200_A0_A1_cache_fns) | |||
436 | .long xscale_dma_a0_map_area | 434 | .long xscale_dma_a0_map_area |
437 | .long xscale_dma_unmap_area | 435 | .long xscale_dma_unmap_area |
438 | .long xscale_dma_flush_range | 436 | .long xscale_dma_flush_range |
439 | .long xscale_dma_clean_range | ||
440 | .long xscale_dma_flush_range | ||
441 | 437 | ||
442 | ENTRY(cpu_xscale_dcache_clean_area) | 438 | ENTRY(cpu_xscale_dcache_clean_area) |
443 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 439 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |