diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-11-26 07:56:21 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-12-14 09:53:22 -0500 |
commit | 2c9b9c8490b60428fa2d1c64042f7c7caed93940 (patch) | |
tree | c8af289af8c801193eea924db0cd81f09068ddb9 /arch/arm/mm/proc-xscale.S | |
parent | ccaf5f05b218e5eb41e2f5cdfd26b18dce4a0218 (diff) |
ARM: add size argument to __cpuc_flush_dcache_page
... and rename the function since it no longer operates on just
pages.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-xscale.S')
-rw-r--r-- | arch/arm/mm/proc-xscale.S | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index f056c283682d..93df47265f2d 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S | |||
@@ -284,15 +284,16 @@ ENTRY(xscale_coherent_user_range) | |||
284 | mov pc, lr | 284 | mov pc, lr |
285 | 285 | ||
286 | /* | 286 | /* |
287 | * flush_kern_dcache_page(void *page) | 287 | * flush_kern_dcache_area(void *addr, size_t size) |
288 | * | 288 | * |
289 | * Ensure no D cache aliasing occurs, either with itself or | 289 | * Ensure no D cache aliasing occurs, either with itself or |
290 | * the I cache | 290 | * the I cache |
291 | * | 291 | * |
292 | * - addr - page aligned address | 292 | * - addr - kernel address |
293 | * - size - region size | ||
293 | */ | 294 | */ |
294 | ENTRY(xscale_flush_kern_dcache_page) | 295 | ENTRY(xscale_flush_kern_dcache_area) |
295 | add r1, r0, #PAGE_SZ | 296 | add r1, r0, r1 |
296 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 297 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
297 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | 298 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
298 | add r0, r0, #CACHELINESIZE | 299 | add r0, r0, #CACHELINESIZE |
@@ -368,7 +369,7 @@ ENTRY(xscale_cache_fns) | |||
368 | .long xscale_flush_user_cache_range | 369 | .long xscale_flush_user_cache_range |
369 | .long xscale_coherent_kern_range | 370 | .long xscale_coherent_kern_range |
370 | .long xscale_coherent_user_range | 371 | .long xscale_coherent_user_range |
371 | .long xscale_flush_kern_dcache_page | 372 | .long xscale_flush_kern_dcache_area |
372 | .long xscale_dma_inv_range | 373 | .long xscale_dma_inv_range |
373 | .long xscale_dma_clean_range | 374 | .long xscale_dma_clean_range |
374 | .long xscale_dma_flush_range | 375 | .long xscale_dma_flush_range |
@@ -392,7 +393,7 @@ ENTRY(xscale_80200_A0_A1_cache_fns) | |||
392 | .long xscale_flush_user_cache_range | 393 | .long xscale_flush_user_cache_range |
393 | .long xscale_coherent_kern_range | 394 | .long xscale_coherent_kern_range |
394 | .long xscale_coherent_user_range | 395 | .long xscale_coherent_user_range |
395 | .long xscale_flush_kern_dcache_page | 396 | .long xscale_flush_kern_dcache_area |
396 | .long xscale_dma_flush_range | 397 | .long xscale_dma_flush_range |
397 | .long xscale_dma_clean_range | 398 | .long xscale_dma_clean_range |
398 | .long xscale_dma_flush_range | 399 | .long xscale_dma_flush_range |