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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-07-26 07:22:12 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-07-27 05:48:42 -0400
commit9ca03a21e320a6bf44559323527aba704bcc8772 (patch)
treec3422c49decfdca220c0088938546c49ee71ba64 /arch/arm/mm/proc-xscale.S
parentb8ab5397bcbd92e3fd4a9770e0bf59315fa38dab (diff)
ARM: Factor out common code from cpu_proc_fin()
All implementations of cpu_proc_fin() start by disabling interrupts and then flush caches. Rather than have every processors proc_fin() implementation do this, move it out into generic code - and move the cache flush past setup_mm_for_reboot() (so it can benefit from having caches still enabled.) This allows cpu_proc_fin() to become independent of the L1/L2 cache types, and eventually move the L2 cache flushing into the L2 support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-xscale.S')
-rw-r--r--arch/arm/mm/proc-xscale.S6
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 63037e2162f2..14075979bcba 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -124,15 +124,11 @@ ENTRY(cpu_xscale_proc_init)
124 * cpu_xscale_proc_fin() 124 * cpu_xscale_proc_fin()
125 */ 125 */
126ENTRY(cpu_xscale_proc_fin) 126ENTRY(cpu_xscale_proc_fin)
127 str lr, [sp, #-4]!
128 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
129 msr cpsr_c, r0
130 bl xscale_flush_kern_cache_all @ clean caches
131 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
132 bic r0, r0, #0x1800 @ ...IZ........... 128 bic r0, r0, #0x1800 @ ...IZ...........
133 bic r0, r0, #0x0006 @ .............CA. 129 bic r0, r0, #0x0006 @ .............CA.
134 mcr p15, 0, r0, c1, c0, 0 @ disable caches 130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
135 ldr pc, [sp], #4 131 mov pc, lr
136 132
137/* 133/*
138 * cpu_xscale_reset(loc) 134 * cpu_xscale_reset(loc)