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authorHaojian Zhuang <haojian.zhuang@marvell.com>2009-12-30 10:02:57 -0500
committerEric Miao <eric.y.miao@gmail.com>2010-01-01 02:51:53 -0500
commit548c6af4627f4dcb24512a381193206e09bd6d31 (patch)
treec9431a3b9bd63292b79cf95bea44940946dc1632 /arch/arm/mm/proc-xsc3.S
parentdc8601a224d546bb321b058fc5ecabdb688a3582 (diff)
[ARM] pxa: enable L2 if present in XSC3
Check whether L2 is present or not in XSC3. If it's present, enable L2 immediately. Disabling L2 after L2 is enabled that would result in unpredicatable behavior of XSC3 processor. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/mm/proc-xsc3.S')
-rw-r--r--arch/arm/mm/proc-xsc3.S7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 96456f548798..8e4f6dca8997 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -407,6 +407,13 @@ __xsc3_setup:
407 407
408 adr r5, xsc3_crval 408 adr r5, xsc3_crval
409 ldmia r5, {r5, r6} 409 ldmia r5, {r5, r6}
410
411#ifdef CONFIG_CACHE_XSC3L2
412 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
413 ands r0, r0, #0xf8
414 orrne r6, r6, #(1 << 26) @ enable L2 if present
415#endif
416
410 mrc p15, 0, r0, c1, c0, 0 @ get control register 417 mrc p15, 0, r0, c1, c0, 0 @ get control register
411 bic r0, r0, r5 @ ..V. ..R. .... ..A. 418 bic r0, r0, r5 @ ..V. ..R. .... ..A.
412 orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu) 419 orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)