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author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-11 13:09:45 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-11 13:09:45 -0400 |
commit | 7cc4e87f912bbefa440a51856b8d076e5d1f554a (patch) | |
tree | 1b8df8683f3de37d2e8211ffa8d151f60d59af62 /arch/arm/mm/proc-xsc3.S | |
parent | 5ba2f67afb02c5302b2898949ed6fc3b3d37dcf1 (diff) | |
parent | 69fc7eed5f56bce15b239e5110de2575a6970df4 (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
[ARM] 5300/1: fixup spitz reset during boot
[ARM] 5295/1: make ZONE_DMA optional
[ARM] 5239/1: Palm Zire 72 power management support
[ARM] 5298/1: Drop desc_handle_irq()
[ARM] 5297/1: [KS8695] Fix two compile-time warnings
[ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
[ARM] pxa: allow multi-machine PCMCIA builds
[ARM] pxa: add preliminary CPUFREQ support for PXA3xx
[ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
[ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
[ARM] pxa/zylonite: add support for USB OHCI
[ARM] ohci-pxa27x: use ioremap() and offset for register access
[ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
[ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
[ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
[ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
[ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
[ARM] pxa: simplify DMA register definitions
[ARM] pxa: make additional DCSR bits valid for PXA3xx
[ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
...
Fixed up conflicts in
arch/arm/mach-versatile/core.c
sound/soc/pxa/pxa2xx-ac97.c
sound/soc/pxa/pxa2xx-i2s.c
manually.
Diffstat (limited to 'arch/arm/mm/proc-xsc3.S')
-rw-r--r-- | arch/arm/mm/proc-xsc3.S | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 7bd9e7197f60..04dc8b65401b 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S | |||
@@ -27,7 +27,7 @@ | |||
27 | #include <linux/linkage.h> | 27 | #include <linux/linkage.h> |
28 | #include <linux/init.h> | 28 | #include <linux/init.h> |
29 | #include <asm/assembler.h> | 29 | #include <asm/assembler.h> |
30 | #include <asm/elf.h> | 30 | #include <asm/hwcap.h> |
31 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
32 | #include <asm/pgtable.h> | 32 | #include <asm/pgtable.h> |
33 | #include <asm/pgtable-hwdef.h> | 33 | #include <asm/pgtable-hwdef.h> |
@@ -345,38 +345,38 @@ ENTRY(cpu_xsc3_switch_mm) | |||
345 | * cpu_xsc3_set_pte_ext(ptep, pte, ext) | 345 | * cpu_xsc3_set_pte_ext(ptep, pte, ext) |
346 | * | 346 | * |
347 | * Set a PTE and flush it out | 347 | * Set a PTE and flush it out |
348 | * | ||
349 | */ | 348 | */ |
349 | cpu_xsc3_mt_table: | ||
350 | .long 0x00 @ L_PTE_MT_UNCACHED | ||
351 | .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE | ||
352 | .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH | ||
353 | .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK | ||
354 | .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED | ||
355 | .long 0x00 @ unused | ||
356 | .long 0x00 @ L_PTE_MT_MINICACHE (not present) | ||
357 | .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?) | ||
358 | .long 0x00 @ unused | ||
359 | .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC | ||
360 | .long 0x00 @ unused | ||
361 | .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED | ||
362 | .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED | ||
363 | .long 0x00 @ unused | ||
364 | .long 0x00 @ unused | ||
365 | .long 0x00 @ unused | ||
366 | |||
350 | .align 5 | 367 | .align 5 |
351 | ENTRY(cpu_xsc3_set_pte_ext) | 368 | ENTRY(cpu_xsc3_set_pte_ext) |
352 | str r1, [r0], #-2048 @ linux version | 369 | xscale_set_pte_ext_prologue |
353 | 370 | ||
354 | bic r2, r1, #0xff0 @ keep C, B bits | ||
355 | orr r2, r2, #PTE_TYPE_EXT @ extended page | ||
356 | tst r1, #L_PTE_SHARED @ shared? | 371 | tst r1, #L_PTE_SHARED @ shared? |
357 | orrne r2, r2, #0x200 | 372 | and r1, r1, #L_PTE_MT_MASK |
358 | 373 | adr ip, cpu_xsc3_mt_table | |
359 | eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY | 374 | ldr ip, [ip, r1] |
360 | 375 | orrne r2, r2, #PTE_EXT_COHERENT @ interlock: mask in coherent bit | |
361 | tst r3, #L_PTE_USER @ user? | 376 | bic r2, r2, #0x0c @ clear old C,B bits |
362 | orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w | 377 | orr r2, r2, ip |
363 | 378 | ||
364 | tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty? | 379 | xscale_set_pte_ext_epilogue |
365 | orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w | ||
366 | @ combined with user -> user r/w | ||
367 | |||
368 | @ If it's cacheable, it needs to be in L2 also. | ||
369 | eor ip, r1, #L_PTE_CACHEABLE | ||
370 | tst ip, #L_PTE_CACHEABLE | ||
371 | orreq r2, r2, #PTE_EXT_TEX(0x5) | ||
372 | |||
373 | tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young? | ||
374 | movne r2, #0 @ no -> fault | ||
375 | |||
376 | str r2, [r0] @ hardware version | ||
377 | mov ip, #0 | ||
378 | mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line | ||
379 | mcr p15, 0, ip, c7, c10, 4 @ data write barrier | ||
380 | mov pc, lr | 380 | mov pc, lr |
381 | 381 | ||
382 | .ltorg | 382 | .ltorg |