aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mm/proc-xsc3.S
diff options
context:
space:
mode:
authorMikael Pettersson <mikpe@it.uu.se>2009-10-29 14:46:56 -0400
committerDan Williams <dan.j.williams@intel.com>2009-10-29 14:46:56 -0400
commit345a32296b1f9f6121379e0240915e0e2be2dbf5 (patch)
tree995ad5887af10b11b2cbc48e8936f7f7d9fbb109 /arch/arm/mm/proc-xsc3.S
parent980f2296b5a8dfe589f023fd34229dcfdcf280fa (diff)
iop: implement sched_clock()
This adds a better sched_clock() to the IOP platform, implemented using its new clocksource support. Tested on n2100, compile-tested for all plat-iop machines. [dan.j.williams@intel.com: allow early cp6 access] Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'arch/arm/mm/proc-xsc3.S')
-rw-r--r--arch/arm/mm/proc-xsc3.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 2028f3702881..fab134e29826 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -396,7 +396,7 @@ __xsc3_setup:
396 orr r4, r4, #0x18 @ cache the page table in L2 396 orr r4, r4, #0x18 @ cache the page table in L2
397 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 397 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
398 398
399 mov r0, #0 @ don't allow CP access 399 mov r0, #1 << 6 @ cp6 access for early sched_clock
400 mcr p15, 0, r0, c15, c1, 0 @ write CP access register 400 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
401 401
402 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg 402 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg