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author | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-07 18:40:39 -0500 |
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committer | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-07 18:40:39 -0500 |
commit | ea14fad0d416354a4e9bb1a04f32acba706f9548 (patch) | |
tree | 2c8acc5331f189aef1d40ddce3f40d6be9314e77 /arch/arm/mm/proc-xsc3.S | |
parent | 6ee7e78e7c78d871409ad4df30551c9355be7d0e (diff) | |
parent | 6705cda24fad1cb0ac82ac4f312df8ec735b39b0 (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (76 commits)
[ARM] 4002/1: S3C24XX: leave parent IRQs unmasked
[ARM] 4001/1: S3C24XX: shorten reboot time
[ARM] 3983/2: remove unused argument to __bug()
[ARM] 4000/1: Osiris: add third serial port in
[ARM] 3999/1: RX3715: suspend to RAM support
[ARM] 3998/1: VR1000: LED platform devices
[ARM] 3995/1: iop13xx: add iop13xx support
[ARM] 3968/1: iop13xx: add iop13xx_defconfig
[ARM] Update mach-types
[ARM] Allow gcc to optimise arm_add_memory a little more
[ARM] 3991/1: i.MX/MX1 high resolution time source
[ARM] 3990/1: i.MX/MX1 more precise PLL decode
[ARM] 3986/1: H1940: suspend to RAM support
[ARM] 3985/1: ixp4xx clocksource cleanup
[ARM] 3984/1: ixp4xx/nslu2: Fix disk LED numbering (take 2)
[ARM] 3994/1: ixp23xx: fix handling of pci master aborts
[ARM] 3981/1: sched_clock for PXA2xx
[ARM] 3980/1: extend the ARM Versatile sched_clock implementation from 32 to 63 bit
[ARM] 3979/1: extend the SA11x0 sched_clock implementation from 32 to 63 bit period
[ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counter
...
Diffstat (limited to 'arch/arm/mm/proc-xsc3.S')
-rw-r--r-- | arch/arm/mm/proc-xsc3.S | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 4ace2d8090c7..1ef564d0957f 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S | |||
@@ -27,7 +27,7 @@ | |||
27 | #include <linux/linkage.h> | 27 | #include <linux/linkage.h> |
28 | #include <linux/init.h> | 28 | #include <linux/init.h> |
29 | #include <asm/assembler.h> | 29 | #include <asm/assembler.h> |
30 | #include <asm/procinfo.h> | 30 | #include <asm/elf.h> |
31 | #include <asm/hardware.h> | 31 | #include <asm/hardware.h> |
32 | #include <asm/pgtable.h> | 32 | #include <asm/pgtable.h> |
33 | #include <asm/pgtable-hwdef.h> | 33 | #include <asm/pgtable-hwdef.h> |
@@ -57,11 +57,6 @@ | |||
57 | #define L2_CACHE_ENABLE 1 | 57 | #define L2_CACHE_ENABLE 1 |
58 | 58 | ||
59 | /* | 59 | /* |
60 | * Enable the Branch Target Buffer (can cause crashes, see erratum #42.) | ||
61 | */ | ||
62 | #define BTB_ENABLE 0 | ||
63 | |||
64 | /* | ||
65 | * This macro is used to wait for a CP15 write and is needed | 60 | * This macro is used to wait for a CP15 write and is needed |
66 | * when we have to ensure that the last operation to the co-pro | 61 | * when we have to ensure that the last operation to the co-pro |
67 | * was completed before continuing with operation. | 62 | * was completed before continuing with operation. |
@@ -371,8 +366,10 @@ ENTRY(cpu_xsc3_switch_mm) | |||
371 | ENTRY(cpu_xsc3_set_pte) | 366 | ENTRY(cpu_xsc3_set_pte) |
372 | str r1, [r0], #-2048 @ linux version | 367 | str r1, [r0], #-2048 @ linux version |
373 | 368 | ||
374 | bic r2, r1, #0xdf0 @ Keep C, B, coherency bits | 369 | bic r2, r1, #0xff0 @ Keep C, B bits |
375 | orr r2, r2, #PTE_TYPE_EXT @ extended page | 370 | orr r2, r2, #PTE_TYPE_EXT @ extended page |
371 | tst r1, #L_PTE_SHARED @ Shared? | ||
372 | orrne r2, r2, #0x200 | ||
376 | 373 | ||
377 | eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY | 374 | eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY |
378 | 375 | ||
@@ -432,9 +429,7 @@ __xsc3_setup: | |||
432 | mrc p15, 0, r0, c1, c0, 0 @ get control register | 429 | mrc p15, 0, r0, c1, c0, 0 @ get control register |
433 | bic r0, r0, r5 @ .... .... .... ..A. | 430 | bic r0, r0, r5 @ .... .... .... ..A. |
434 | orr r0, r0, r6 @ .... .... .... .C.M | 431 | orr r0, r0, r6 @ .... .... .... .C.M |
435 | #if BTB_ENABLE | ||
436 | orr r0, r0, #0x00000800 @ ..VI Z..S .... .... | 432 | orr r0, r0, #0x00000800 @ ..VI Z..S .... .... |
437 | #endif | ||
438 | #if L2_CACHE_ENABLE | 433 | #if L2_CACHE_ENABLE |
439 | orr r0, r0, #0x04000000 @ L2 enable | 434 | orr r0, r0, #0x04000000 @ L2 enable |
440 | #endif | 435 | #endif |