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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-07-26 07:22:12 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-07-27 05:48:42 -0400
commit9ca03a21e320a6bf44559323527aba704bcc8772 (patch)
treec3422c49decfdca220c0088938546c49ee71ba64 /arch/arm/mm/proc-xsc3.S
parentb8ab5397bcbd92e3fd4a9770e0bf59315fa38dab (diff)
ARM: Factor out common code from cpu_proc_fin()
All implementations of cpu_proc_fin() start by disabling interrupts and then flush caches. Rather than have every processors proc_fin() implementation do this, move it out into generic code - and move the cache flush past setup_mm_for_reboot() (so it can benefit from having caches still enabled.) This allows cpu_proc_fin() to become independent of the L1/L2 cache types, and eventually move the L2 cache flushing into the L2 support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-xsc3.S')
-rw-r--r--arch/arm/mm/proc-xsc3.S6
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index e5797f1c1db7..361a51e49030 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -90,15 +90,11 @@ ENTRY(cpu_xsc3_proc_init)
90 * cpu_xsc3_proc_fin() 90 * cpu_xsc3_proc_fin()
91 */ 91 */
92ENTRY(cpu_xsc3_proc_fin) 92ENTRY(cpu_xsc3_proc_fin)
93 str lr, [sp, #-4]!
94 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
95 msr cpsr_c, r0
96 bl xsc3_flush_kern_cache_all @ clean caches
97 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 93 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
98 bic r0, r0, #0x1800 @ ...IZ........... 94 bic r0, r0, #0x1800 @ ...IZ...........
99 bic r0, r0, #0x0006 @ .............CA. 95 bic r0, r0, #0x0006 @ .............CA.
100 mcr p15, 0, r0, c1, c0, 0 @ disable caches 96 mcr p15, 0, r0, c1, c0, 0 @ disable caches
101 ldr pc, [sp], #4 97 mov pc, lr
102 98
103/* 99/*
104 * cpu_xsc3_reset(loc) 100 * cpu_xsc3_reset(loc)