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authorWill Deacon <will.deacon@arm.com>2010-09-14 04:51:43 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-09-17 05:16:51 -0400
commit9f05027c7cb3cfe56a31892bd83391138d41a667 (patch)
treeefe9361be8e1b8d78ff44ef13a1e46e1a4b9b23a /arch/arm/mm/proc-v7.S
parent6491848d1ab246f6d243ddef25085fc1d836ff2c (diff)
ARM: 6388/1: errata: DMB operation may be faulty
On versions of the Cortex-A9 up to and including r2p2, under rare circumstances, a DMB instruction between 2 write operations may not ensure the correct visibility ordering of the 2 writes. This workaround sets a bit in the diagnostic register of the Cortex-A9, causing the DMB instruction to behave like a DSB, which functions correctly on the affected cores. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r--arch/arm/mm/proc-v7.S16
1 files changed, 14 insertions, 2 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 1f16f9e3f441..945f36341fa6 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -201,7 +201,7 @@ __v7_setup:
201 mrc p15, 0, r0, c0, c0, 0 @ read main ID register 201 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
202 and r10, r0, #0xff000000 @ ARM? 202 and r10, r0, #0xff000000 @ ARM?
203 teq r10, #0x41000000 203 teq r10, #0x41000000
204 bne 2f 204 bne 3f
205 and r5, r0, #0x00f00000 @ variant 205 and r5, r0, #0x00f00000 @ variant
206 and r6, r0, #0x0000000f @ revision 206 and r6, r0, #0x0000000f @ revision
207 orr r6, r6, r5, lsr #20-4 @ combine variant and revision 207 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
@@ -231,8 +231,20 @@ __v7_setup:
231 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 231 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
232 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 232 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
233#endif 233#endif
234 b 3f
235
236 /* Cortex-A9 Errata */
2372: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
238 teq r0, r10
239 bne 3f
240#ifdef CONFIG_ARM_ERRATA_742230
241 cmp r6, #0x22 @ only present up to r2p2
242 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
243 orrle r10, r10, #1 << 4 @ set bit #4
244 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
245#endif
234 246
2352: mov r10, #0 2473: mov r10, #0
236#ifdef HARVARD_CACHE 248#ifdef HARVARD_CACHE
237 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 249 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
238#endif 250#endif