diff options
author | Daniel Walker <dwalker@fifo99.com> | 2010-09-17 11:42:10 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-09-17 11:44:24 -0400 |
commit | 14eff1812679c76564b775aa95cdd378965f6cfb (patch) | |
tree | af574c59bddc14386830a7e93d63a8a7c29a4904 /arch/arm/mm/proc-v7.S | |
parent | b2b163bb82b12bae2504a5b31399c37d099ad3cc (diff) |
ARM: 6398/1: add proc info for ARM11MPCore/Cortex-A9 from ARM
Setting of these bits can cause issues on other SMP SoC's not produced
by ARM.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r-- | arch/arm/mm/proc-v7.S | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 080129263eef..7563ff0141bd 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -186,13 +186,14 @@ cpu_v7_name: | |||
186 | * It is assumed that: | 186 | * It is assumed that: |
187 | * - cache type register is implemented | 187 | * - cache type register is implemented |
188 | */ | 188 | */ |
189 | __v7_setup: | 189 | __v7_ca9mp_setup: |
190 | #ifdef CONFIG_SMP | 190 | #ifdef CONFIG_SMP |
191 | mrc p15, 0, r0, c1, c0, 1 | 191 | mrc p15, 0, r0, c1, c0, 1 |
192 | tst r0, #(1 << 6) @ SMP/nAMP mode enabled? | 192 | tst r0, #(1 << 6) @ SMP/nAMP mode enabled? |
193 | orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and | 193 | orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and |
194 | mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting | 194 | mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting |
195 | #endif | 195 | #endif |
196 | __v7_setup: | ||
196 | adr r12, __v7_setup_stack @ the local stack | 197 | adr r12, __v7_setup_stack @ the local stack |
197 | stmia r12, {r0-r5, r7, r9, r11, lr} | 198 | stmia r12, {r0-r5, r7, r9, r11, lr} |
198 | bl v7_flush_dcache_all | 199 | bl v7_flush_dcache_all |
@@ -349,6 +350,29 @@ cpu_elf_name: | |||
349 | 350 | ||
350 | .section ".proc.info.init", #alloc, #execinstr | 351 | .section ".proc.info.init", #alloc, #execinstr |
351 | 352 | ||
353 | .type __v7_ca9mp_proc_info, #object | ||
354 | __v7_ca9mp_proc_info: | ||
355 | .long 0x410fc090 @ Required ID value | ||
356 | .long 0xff0ffff0 @ Mask for ID | ||
357 | .long PMD_TYPE_SECT | \ | ||
358 | PMD_SECT_AP_WRITE | \ | ||
359 | PMD_SECT_AP_READ | \ | ||
360 | PMD_FLAGS | ||
361 | .long PMD_TYPE_SECT | \ | ||
362 | PMD_SECT_XN | \ | ||
363 | PMD_SECT_AP_WRITE | \ | ||
364 | PMD_SECT_AP_READ | ||
365 | b __v7_ca9mp_setup | ||
366 | .long cpu_arch_name | ||
367 | .long cpu_elf_name | ||
368 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP | ||
369 | .long cpu_v7_name | ||
370 | .long v7_processor_functions | ||
371 | .long v7wbi_tlb_fns | ||
372 | .long v6_user_fns | ||
373 | .long v7_cache_fns | ||
374 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info | ||
375 | |||
352 | /* | 376 | /* |
353 | * Match any ARMv7 processor core. | 377 | * Match any ARMv7 processor core. |
354 | */ | 378 | */ |