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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-09-04 05:47:48 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-10-04 15:23:36 -0400
commitf00ec48fadf5e37e7889f14cff900aa70d18b644 (patch)
tree421cbce97167a78532aa825624f380caade3c0d2 /arch/arm/mm/proc-v7.S
parent067173526c3bbc2eaeefcf6b7b2a9d998b9e8042 (diff)
ARM: Allow SMP kernels to boot on UP systems
UP systems do not implement all the instructions that SMP systems have, so in order to boot a SMP kernel on a UP system, we need to rewrite parts of the kernel. Do this using an 'alternatives' scheme, where the kernel code and data is modified prior to initialization to replace the SMP instructions, thereby rendering the problematical code ineffectual. We use the linker to generate a list of 32-bit word locations and their replacement values, and run through these replacements when we detect a UP system. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r--arch/arm/mm/proc-v7.S41
1 files changed, 27 insertions, 14 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7563ff0141bd..df422fee1cb6 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
30#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 30#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 31#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
32 32
33#ifndef CONFIG_SMP
34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 33/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB 34#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
36#define PMD_FLAGS PMD_SECT_WB 35#define PMD_FLAGS_UP PMD_SECT_WB
37#else 36
38/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
39#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 38#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S 39#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
41#endif
42 40
43ENTRY(cpu_v7_proc_init) 41ENTRY(cpu_v7_proc_init)
44 mov pc, lr 42 mov pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
105#ifdef CONFIG_MMU 103#ifdef CONFIG_MMU
106 mov r2, #0 104 mov r2, #0
107 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 105 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
108 orr r0, r0, #TTB_FLAGS 106 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
107 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
109#ifdef CONFIG_ARM_ERRATA_430973 108#ifdef CONFIG_ARM_ERRATA_430973
110 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
111#endif 110#endif
@@ -188,7 +187,8 @@ cpu_v7_name:
188 */ 187 */
189__v7_ca9mp_setup: 188__v7_ca9mp_setup:
190#ifdef CONFIG_SMP 189#ifdef CONFIG_SMP
191 mrc p15, 0, r0, c1, c0, 1 190 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
191 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
192 tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 192 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
193 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and 193 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
194 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting 194 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
@@ -262,7 +262,8 @@ __v7_setup:
262#ifdef CONFIG_MMU 262#ifdef CONFIG_MMU
263 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 263 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
264 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 264 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
265 orr r4, r4, #TTB_FLAGS 265 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
266 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
266 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 267 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
267 mov r10, #0x1f @ domains 0, 1 = manager 268 mov r10, #0x1f @ domains 0, 1 = manager
268 mcr p15, 0, r10, c3, c0, 0 @ load domain access register 269 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
@@ -354,10 +355,16 @@ cpu_elf_name:
354__v7_ca9mp_proc_info: 355__v7_ca9mp_proc_info:
355 .long 0x410fc090 @ Required ID value 356 .long 0x410fc090 @ Required ID value
356 .long 0xff0ffff0 @ Mask for ID 357 .long 0xff0ffff0 @ Mask for ID
357 .long PMD_TYPE_SECT | \ 358 ALT_SMP(.long \
359 PMD_TYPE_SECT | \
360 PMD_SECT_AP_WRITE | \
361 PMD_SECT_AP_READ | \
362 PMD_FLAGS_SMP)
363 ALT_UP(.long \
364 PMD_TYPE_SECT | \
358 PMD_SECT_AP_WRITE | \ 365 PMD_SECT_AP_WRITE | \
359 PMD_SECT_AP_READ | \ 366 PMD_SECT_AP_READ | \
360 PMD_FLAGS 367 PMD_FLAGS_UP)
361 .long PMD_TYPE_SECT | \ 368 .long PMD_TYPE_SECT | \
362 PMD_SECT_XN | \ 369 PMD_SECT_XN | \
363 PMD_SECT_AP_WRITE | \ 370 PMD_SECT_AP_WRITE | \
@@ -380,10 +387,16 @@ __v7_ca9mp_proc_info:
380__v7_proc_info: 387__v7_proc_info:
381 .long 0x000f0000 @ Required ID value 388 .long 0x000f0000 @ Required ID value
382 .long 0x000f0000 @ Mask for ID 389 .long 0x000f0000 @ Mask for ID
383 .long PMD_TYPE_SECT | \ 390 ALT_SMP(.long \
391 PMD_TYPE_SECT | \
392 PMD_SECT_AP_WRITE | \
393 PMD_SECT_AP_READ | \
394 PMD_FLAGS_SMP)
395 ALT_UP(.long \
396 PMD_TYPE_SECT | \
384 PMD_SECT_AP_WRITE | \ 397 PMD_SECT_AP_WRITE | \
385 PMD_SECT_AP_READ | \ 398 PMD_SECT_AP_READ | \
386 PMD_FLAGS 399 PMD_FLAGS_UP)
387 .long PMD_TYPE_SECT | \ 400 .long PMD_TYPE_SECT | \
388 PMD_SECT_XN | \ 401 PMD_SECT_XN | \
389 PMD_SECT_AP_WRITE | \ 402 PMD_SECT_AP_WRITE | \