[ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data

This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It
configures the L2 cache auxiliary control register so that the Write
Allocate mode for the L2 cache is disabled.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 5 insertions, 0 deletions

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 370baa7a0f08..f2305441e7d1 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -194,6 +194,11 @@ __v7_setup:
         orr     r10, r10, #(1 << 9)             @ set PLDNOP to 1
         mcr     p15, 0, r10, c1, c0, 1          @ write aux control register
 #endif
+#ifdef CONFIG_ARM_ERRATA_460075
+        mrc     p15, 1, r10, c9, c0, 2          @ read L2 cache aux ctrl register
+        orr     r10, r10, #(1 << 22)            @ set the Write Allocate disable bit
+        mcr     p15, 1, r10, c9, c0, 2          @ write the L2 cache aux ctrl register
+#endif
         mov     r10, #0
 #ifdef HARVARD_CACHE
         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate