diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2009-04-30 12:06:20 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-04-30 15:13:00 -0400 |
commit | 0516e4643cd22fc9f535aef02ad1de66c382c93b (patch) | |
tree | 8b82945aa5f1ef825656aed2580cacafcd829ac3 /arch/arm/mm/proc-v7.S | |
parent | 855c551f5b8cc3815d58e1056c1f1e7c461e2d24 (diff) |
[ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data
This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It
configures the L2 cache auxiliary control register so that the Write
Allocate mode for the L2 cache is disabled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r-- | arch/arm/mm/proc-v7.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 370baa7a0f08..f2305441e7d1 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -194,6 +194,11 @@ __v7_setup: | |||
194 | orr r10, r10, #(1 << 9) @ set PLDNOP to 1 | 194 | orr r10, r10, #(1 << 9) @ set PLDNOP to 1 |
195 | mcr p15, 0, r10, c1, c0, 1 @ write aux control register | 195 | mcr p15, 0, r10, c1, c0, 1 @ write aux control register |
196 | #endif | 196 | #endif |
197 | #ifdef CONFIG_ARM_ERRATA_460075 | ||
198 | mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register | ||
199 | orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit | ||
200 | mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register | ||
201 | #endif | ||
197 | mov r10, #0 | 202 | mov r10, #0 |
198 | #ifdef HARVARD_CACHE | 203 | #ifdef HARVARD_CACHE |
199 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate | 204 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |