ARM: pm: only use preallocated page table during resume

Only use the preallocated page table during the resume, not while
suspending.  This avoids the overhead of having to switch unnecessarily
to the resume page table in the suspend path.

Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 17 insertions, 16 deletions

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 21d6910d2208..b56004f90d93 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -217,22 +217,21 @@ ENDPROC(cpu_v7_set_pte_ext)
 
 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 .globl  cpu_v7_suspend_size
-.equ    cpu_v7_suspend_size, 4 * 9
+.equ    cpu_v7_suspend_size, 4 * 8
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_v7_do_suspend)
-        stmfd   sp!, {r4 - r11, lr}
+        stmfd   sp!, {r4 - r10, lr}
         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
         mrc     p15, 0, r5, c13, c0, 1  @ Context ID
         mrc     p15, 0, r6, c13, c0, 3  @ User r/o thread ID
         stmia   r0!, {r4 - r6}
         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
-        mrc     p15, 0, r7, c2, c0, 0   @ TTB 0
-        mrc     p15, 0, r8, c2, c0, 1   @ TTB 1
-        mrc     p15, 0, r9, c1, c0, 0   @ Control register
-        mrc     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
-        mrc     p15, 0, r11, c1, c0, 2  @ Co-processor access control
-        stmia   r0, {r6 - r11}
-        ldmfd   sp!, {r4 - r11, pc}
+        mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
+        mrc     p15, 0, r8, c1, c0, 0   @ Control register
+        mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
+        mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
+        stmia   r0, {r6 - r10}
+        ldmfd   sp!, {r4 - r10, pc}
 ENDPROC(cpu_v7_do_suspend)
 
 ENTRY(cpu_v7_do_resume)
@@ -243,22 +242,24 @@ ENTRY(cpu_v7_do_resume)
         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
         mcr     p15, 0, r5, c13, c0, 1  @ Context ID
         mcr     p15, 0, r6, c13, c0, 3  @ User r/o thread ID
-        ldmia   r0, {r6 - r11}
+        ldmia   r0, {r6 - r10}
         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
-        mcr     p15, 0, r7, c2, c0, 0   @ TTB 0
-        mcr     p15, 0, r8, c2, c0, 1   @ TTB 1
+        ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
+        ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
+        mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
+        mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
         mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
         mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
-        teq     r4, r10                 @ Is it already set?
-        mcrne   p15, 0, r10, c1, c0, 1  @ No, so write it
-        mcr     p15, 0, r11, c1, c0, 2  @ Co-processor access control
+        teq     r4, r9                  @ Is it already set?
+        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
+        mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
         ldr     r4, =PRRR               @ PRRR
         ldr     r5, =NMRR               @ NMRR
         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
         isb
         dsb
-        mov     r0, r9                  @ control register
+        mov     r0, r8                  @ control register
         b       cpu_resume_mmu
 ENDPROC(cpu_v7_do_resume)
 #endif