Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (417 commits)
  MAINTAINERS: EB110ATX is not ebsa110
  MAINTAINERS: update Eric Miao's email address and status
  fb: add support of LCD display controller on pxa168/910 (base layer)
  [ARM] 5552/1: ep93xx get_uart_rate(): use EP93XX_SYSCON_PWRCNT and EP93XX_SYSCON_PWRCN
  [ARM] pxa/sharpsl_pm: zaurus needs generic pxa suspend/resume routines
  [ARM] 5544/1: Trust PrimeCell resource sizes
  [ARM] pxa/sharpsl_pm: cleanup of gpio-related code.
  [ARM] pxa/sharpsl_pm: drop set_irq_type calls
  [ARM] pxa/sharpsl_pm: merge pxa-specific code into generic one
  [ARM] pxa/sharpsl_pm: merge the two sharpsl_pm.c since it's now pxa specific
  [ARM] sa1100: remove unused collie_pm.c
  [ARM] pxa: fix the conflicting non-static declarations of global_gpios[]
  [ARM] 5550/1: Add default configure file for w90p910 platform
  [ARM] 5549/1: Add clock api for w90p910 platform.
  [ARM] 5548/1: Add gpio api for w90p910 platform
  [ARM] 5551/1: Add multi-function pin api for w90p910 platform.
  [ARM] Make ARM_VIC_NR depend on ARM_VIC
  [ARM] 5546/1: ARM PL022 SSP/SPI driver v3
  ARM: OMAP4: SMP: Update defconfig for OMAP4430
  ARM: OMAP4: SMP: Enable SMP support for OMAP4430
  ...

1 files changed, 48 insertions, 11 deletions

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a08d9d2380d3..180a08d03a03 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -19,17 +19,23 @@
 
 #include "proc-macros.S"
 
-#define TTB_C           (1 << 0)
 #define TTB_S           (1 << 1)
 #define TTB_RGN_NC      (0 << 3)
 #define TTB_RGN_OC_WBWA (1 << 3)
 #define TTB_RGN_OC_WT   (2 << 3)
 #define TTB_RGN_OC_WB   (3 << 3)
+#define TTB_NOS         (1 << 5)
+#define TTB_IRGN_NC     ((0 << 0) | (0 << 6))
+#define TTB_IRGN_WBWA   ((0 << 0) | (1 << 6))
+#define TTB_IRGN_WT     ((1 << 0) | (0 << 6))
+#define TTB_IRGN_WB     ((1 << 0) | (1 << 6))
 
 #ifndef CONFIG_SMP
-#define TTB_FLAGS       TTB_C|TTB_RGN_OC_WB             @ mark PTWs cacheable, outer WB
+/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
+#define TTB_FLAGS       TTB_IRGN_WB|TTB_RGN_OC_WB
 #else
-#define TTB_FLAGS       TTB_C|TTB_S|TTB_RGN_OC_WBWA     @ mark PTWs cacheable and shared, outer WBWA
+/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
+#define TTB_FLAGS       TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
 #endif
 
 ENTRY(cpu_v7_proc_init)
@@ -176,8 +182,8 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
-        mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
-        orr     r0, r0, #(0x1 << 6)
+        mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode and
+        orr     r0, r0, #(1 << 6) | (1 << 0)    @ TLB ops broadcasting
         mcr     p15, 0, r0, c1, c0, 1
 #endif
         adr     r12, __v7_setup_stack           @ the local stack
@@ -227,12 +233,43 @@ __v7_setup:
         mov     r10, #0x1f                      @ domains 0, 1 = manager
         mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
 #endif
-        ldr     r5, =0xff0aa1a8
-        ldr     r6, =0x40e040e0
+        /*
+         * Memory region attributes with SCTLR.TRE=1
+         *
+         *   n = TEX[0],C,B
+         *   TR = PRRR[2n+1:2n]         - memory type
+         *   IR = NMRR[2n+1:2n]         - inner cacheable property
+         *   OR = NMRR[2n+17:2n+16]     - outer cacheable property
+         *
+         *                      n       TR      IR      OR
+         *   UNCACHED           000     00
+         *   BUFFERABLE         001     10      00      00
+         *   WRITETHROUGH       010     10      10      10
+         *   WRITEBACK          011     10      11      11
+         *   reserved           110
+         *   WRITEALLOC         111     10      01      01
+         *   DEV_SHARED         100     01
+         *   DEV_NONSHARED      100     01
+         *   DEV_WC             001     10
+         *   DEV_CACHED         011     10
+         *
+         * Other attributes:
+         *
+         *   DS0 = PRRR[16] = 0         - device shareable property
+         *   DS1 = PRRR[17] = 1         - device shareable property
+         *   NS0 = PRRR[18] = 0         - normal shareable property
+         *   NS1 = PRRR[19] = 1         - normal shareable property
+         *   NOS = PRRR[24+n] = 1       - not outer shareable
+         */
+        ldr     r5, =0xff0a81a8                 @ PRRR
+        ldr     r6, =0x40e040e0                 @ NMRR
         mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
         adr     r5, v7_crval
         ldmia   r5, {r5, r6}
+#ifdef CONFIG_CPU_ENDIAN_BE8
+        orr     r6, r6, #1 << 25                @ big-endian page tables
+#endif
         mrc     p15, 0, r0, c1, c0, 0           @ read control register
         bic     r0, r0, r5                      @ clear bits them
         orr     r0, r0, r6                      @ set them
@@ -240,14 +277,14 @@ __v7_setup:
 ENDPROC(__v7_setup)
 
         /*   AT
-         *  TFR   EV X F   I D LR
-         * .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM
+         *  TFR   EV X F   I D LR    S
+         * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
          * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
-         *    1    0 110       0011 1.00 .111 1101 < we want
+         *    1    0 110       0011 1100 .111 1101 < we want
          */
         .type   v7_crval, #object
 v7_crval:
-        crval   clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
+        crval   clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
 
 __v7_setup_stack:
         .space  4 * 11                          @ 11 registers