diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2011-11-22 12:30:29 -0500 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2011-12-08 05:30:39 -0500 |
commit | 1b6ba46b7efa31055eb993a6f2c6bbcb8b35b001 (patch) | |
tree | b04e3b1fd23ba81a643f64cba113551d127111a0 /arch/arm/mm/proc-v7.S | |
parent | da02877987e6e173ebba137d4e1e155e1f1151cd (diff) |
ARM: LPAE: MMU setup for the 3-level page table format
This patch adds the MMU initialisation for the LPAE page table format.
The swapper_pg_dir size with LPAE is 5 rather than 4 pages. A new
proc-v7-3level.S file contains the TTB initialisation, context switch
and PTE setting code with the LPAE. The TTBRx split is based on the
PAGE_OFFSET with TTBR1 used for the kernel mappings. The 36-bit mappings
(supersections) and a few other memory types in mmu.c are conditionally
compiled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r-- | arch/arm/mm/proc-v7.S | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index ed1a4d115331..7efa2a721d5d 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -19,7 +19,11 @@ | |||
19 | 19 | ||
20 | #include "proc-macros.S" | 20 | #include "proc-macros.S" |
21 | 21 | ||
22 | #ifdef CONFIG_ARM_LPAE | ||
23 | #include "proc-v7-3level.S" | ||
24 | #else | ||
22 | #include "proc-v7-2level.S" | 25 | #include "proc-v7-2level.S" |
26 | #endif | ||
23 | 27 | ||
24 | ENTRY(cpu_v7_proc_init) | 28 | ENTRY(cpu_v7_proc_init) |
25 | mov pc, lr | 29 | mov pc, lr |
@@ -87,7 +91,7 @@ ENDPROC(cpu_v7_dcache_clean_area) | |||
87 | 91 | ||
88 | /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ | 92 | /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ |
89 | .globl cpu_v7_suspend_size | 93 | .globl cpu_v7_suspend_size |
90 | .equ cpu_v7_suspend_size, 4 * 7 | 94 | .equ cpu_v7_suspend_size, 4 * 8 |
91 | #ifdef CONFIG_ARM_CPU_SUSPEND | 95 | #ifdef CONFIG_ARM_CPU_SUSPEND |
92 | ENTRY(cpu_v7_do_suspend) | 96 | ENTRY(cpu_v7_do_suspend) |
93 | stmfd sp!, {r4 - r10, lr} | 97 | stmfd sp!, {r4 - r10, lr} |
@@ -96,10 +100,11 @@ ENTRY(cpu_v7_do_suspend) | |||
96 | stmia r0!, {r4 - r5} | 100 | stmia r0!, {r4 - r5} |
97 | mrc p15, 0, r6, c3, c0, 0 @ Domain ID | 101 | mrc p15, 0, r6, c3, c0, 0 @ Domain ID |
98 | mrc p15, 0, r7, c2, c0, 1 @ TTB 1 | 102 | mrc p15, 0, r7, c2, c0, 1 @ TTB 1 |
103 | mrc p15, 0, r11, c2, c0, 2 @ TTB control register | ||
99 | mrc p15, 0, r8, c1, c0, 0 @ Control register | 104 | mrc p15, 0, r8, c1, c0, 0 @ Control register |
100 | mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register | 105 | mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register |
101 | mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control | 106 | mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control |
102 | stmia r0, {r6 - r10} | 107 | stmia r0, {r6 - r11} |
103 | ldmfd sp!, {r4 - r10, pc} | 108 | ldmfd sp!, {r4 - r10, pc} |
104 | ENDPROC(cpu_v7_do_suspend) | 109 | ENDPROC(cpu_v7_do_suspend) |
105 | 110 | ||
@@ -111,13 +116,15 @@ ENTRY(cpu_v7_do_resume) | |||
111 | ldmia r0!, {r4 - r5} | 116 | ldmia r0!, {r4 - r5} |
112 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID | 117 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID |
113 | mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID | 118 | mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID |
114 | ldmia r0, {r6 - r10} | 119 | ldmia r0, {r6 - r11} |
115 | mcr p15, 0, r6, c3, c0, 0 @ Domain ID | 120 | mcr p15, 0, r6, c3, c0, 0 @ Domain ID |
121 | #ifndef CONFIG_ARM_LPAE | ||
116 | ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) | 122 | ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) |
117 | ALT_UP(orr r1, r1, #TTB_FLAGS_UP) | 123 | ALT_UP(orr r1, r1, #TTB_FLAGS_UP) |
124 | #endif | ||
118 | mcr p15, 0, r1, c2, c0, 0 @ TTB 0 | 125 | mcr p15, 0, r1, c2, c0, 0 @ TTB 0 |
119 | mcr p15, 0, r7, c2, c0, 1 @ TTB 1 | 126 | mcr p15, 0, r7, c2, c0, 1 @ TTB 1 |
120 | mcr p15, 0, ip, c2, c0, 2 @ TTB control register | 127 | mcr p15, 0, r11, c2, c0, 2 @ TTB control register |
121 | mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register | 128 | mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register |
122 | teq r4, r9 @ Is it already set? | 129 | teq r4, r9 @ Is it already set? |
123 | mcrne p15, 0, r9, c1, c0, 1 @ No, so write it | 130 | mcrne p15, 0, r9, c1, c0, 1 @ No, so write it |
@@ -291,11 +298,11 @@ __v7_setup_stack: | |||
291 | */ | 298 | */ |
292 | .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 | 299 | .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 |
293 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ | 300 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ |
294 | PMD_FLAGS_SMP | \mm_mmuflags) | 301 | PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) |
295 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ | 302 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ |
296 | PMD_FLAGS_UP | \mm_mmuflags) | 303 | PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags) |
297 | .long PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \ | 304 | .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \ |
298 | PMD_SECT_AP_READ | \io_mmuflags | 305 | PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags |
299 | W(b) \initfunc | 306 | W(b) \initfunc |
300 | .long cpu_arch_name | 307 | .long cpu_arch_name |
301 | .long cpu_elf_name | 308 | .long cpu_elf_name |
@@ -308,6 +315,7 @@ __v7_setup_stack: | |||
308 | .long v7_cache_fns | 315 | .long v7_cache_fns |
309 | .endm | 316 | .endm |
310 | 317 | ||
318 | #ifndef CONFIG_ARM_LPAE | ||
311 | /* | 319 | /* |
312 | * ARM Ltd. Cortex A5 processor. | 320 | * ARM Ltd. Cortex A5 processor. |
313 | */ | 321 | */ |
@@ -327,6 +335,7 @@ __v7_ca9mp_proc_info: | |||
327 | .long 0xff0ffff0 | 335 | .long 0xff0ffff0 |
328 | __v7_proc __v7_ca9mp_setup | 336 | __v7_proc __v7_ca9mp_setup |
329 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info | 337 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info |
338 | #endif /* CONFIG_ARM_LPAE */ | ||
330 | 339 | ||
331 | /* | 340 | /* |
332 | * ARM Ltd. Cortex A15 processor. | 341 | * ARM Ltd. Cortex A15 processor. |