ARM: LPAE: accomodate >32-bit addresses for page table base

This patch redefines the early boot time use of the R4 register to steal a few
low order bits (ARCH_PGD_SHIFT bits) on LPAE systems.  This allows for up to
38-bit physical addresses.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Subash Patel <subash.rp@samsung.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 58ab7477bb61..5ffe1956c6d9 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -114,6 +114,7 @@ ENDPROC(cpu_v7_set_pte_ext)
          */
         .macro  v7_ttb_setup, zero, ttbr0, ttbr1, tmp
         ldr     \tmp, =swapper_pg_dir           @ swapper_pg_dir virtual address
+        mov     \tmp, \tmp, lsr #ARCH_PGD_SHIFT
         cmp     \ttbr1, \tmp                    @ PHYS_OFFSET > PAGE_OFFSET?
         mrc     p15, 0, \tmp, c2, c0, 2         @ TTB control register
         orr     \tmp, \tmp, #TTB_EAE
@@ -128,8 +129,15 @@ ENDPROC(cpu_v7_set_pte_ext)
          */
         orrls   \tmp, \tmp, #TTBR1_SIZE                         @ TTBCR.T1SZ
         mcr     p15, 0, \tmp, c2, c0, 2                         @ TTBCR
+        mov     \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
+        mov     \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT             @ lower bits
         addls   \ttbr1, \ttbr1, #TTBR1_OFFSET
         mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
+        mov     \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
+        mov     \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT             @ lower bits
+        mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
+        mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
+        mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
         .endm
 
         __CPUINIT