ARM: pm: add generic CPU suspend/resume support

This adds core support for saving and restoring CPU coprocessor
registers for suspend/resume support.  This contains support for suspend
with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
Tested on Assabet and Tegra 2.

Tested-by: Colin Cross <ccross@android.com>
Tested-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 50 insertions, 0 deletions

diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 59a7e1ffe7bc..832b6bdc192c 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -121,6 +121,53 @@ ENTRY(cpu_v6_set_pte_ext)
 #endif
         mov     pc, lr
 
+/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
+.globl  cpu_v6_suspend_size
+.equ    cpu_v6_suspend_size, 4 * 8
+#ifdef CONFIG_PM
+ENTRY(cpu_v6_do_suspend)
+        stmfd   sp!, {r4 - r11, lr}
+        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+        mrc     p15, 0, r5, c13, c0, 1  @ Context ID
+        mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
+        mrc     p15, 0, r7, c2, c0, 0   @ Translation table base 0
+        mrc     p15, 0, r8, c2, c0, 1   @ Translation table base 1
+        mrc     p15, 0, r9, c1, c0, 1   @ auxillary control register
+        mrc     p15, 0, r10, c1, c0, 2  @ co-processor access control
+        mrc     p15, 0, r11, c1, c0, 0  @ control register
+        stmia   r0, {r4 - r11}
+        ldmfd   sp!, {r4- r11, pc}
+ENDPROC(cpu_v6_do_suspend)
+
+ENTRY(cpu_v6_do_resume)
+        mov     ip, #0
+        mcr     p15, 0, ip, c7, c14, 0  @ clean+invalidate D cache
+        mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
+        mcr     p15, 0, ip, c7, c15, 0  @ clean+invalidate cache
+        mcr     p15, 0, ip, c7, c10, 4  @ drain write buffer
+        ldmia   r0, {r4 - r11}
+        mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+        mcr     p15, 0, r5, c13, c0, 1  @ Context ID
+        mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
+        mcr     p15, 0, r7, c2, c0, 0   @ Translation table base 0
+        mcr     p15, 0, r8, c2, c0, 1   @ Translation table base 1
+        mcr     p15, 0, r9, c1, c0, 1   @ auxillary control register
+        mcr     p15, 0, r10, c1, c0, 2  @ co-processor access control
+        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
+        mcr     p15, 0, ip, c7, c5, 4   @ ISB
+        mov     r0, r11                 @ control register
+        mov     r2, r7, lsr #14         @ get TTB0 base
+        mov     r2, r2, lsl #14
+        ldr     r3, cpu_resume_l1_flags
+        b       cpu_resume_mmu
+ENDPROC(cpu_v6_do_resume)
+cpu_resume_l1_flags:
+        ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
+        ALT_UP(.long  PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
+#else
+#define cpu_v6_do_suspend 0
+#define cpu_v6_do_resume 0
+#endif
 
 
         .type   cpu_v6_name, #object
@@ -206,6 +253,9 @@ ENTRY(v6_processor_functions)
         .word   cpu_v6_dcache_clean_area
         .word   cpu_v6_switch_mm
         .word   cpu_v6_set_pte_ext
+        .word   cpu_v6_suspend_size
+        .word   cpu_v6_do_suspend
+        .word   cpu_v6_do_resume
         .size   v6_processor_functions, . - v6_processor_functions
 
         .section ".rodata"