diff options
author | Lucas De Marchi <lucas.demarchi@profusion.mobi> | 2011-03-30 21:57:33 -0400 |
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committer | Lucas De Marchi <lucas.demarchi@profusion.mobi> | 2011-03-31 10:26:23 -0400 |
commit | 25985edcedea6396277003854657b5f3cb31a628 (patch) | |
tree | f026e810210a2ee7290caeb737c23cb6472b7c38 /arch/arm/mm/proc-v6.S | |
parent | 6aba74f2791287ec407e0f92487a725a25908067 (diff) |
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/arm/mm/proc-v6.S')
-rw-r--r-- | arch/arm/mm/proc-v6.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 832b6bdc192c..bfa0c9f611c5 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
@@ -132,7 +132,7 @@ ENTRY(cpu_v6_do_suspend) | |||
132 | mrc p15, 0, r6, c3, c0, 0 @ Domain ID | 132 | mrc p15, 0, r6, c3, c0, 0 @ Domain ID |
133 | mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 | 133 | mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 |
134 | mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 | 134 | mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 |
135 | mrc p15, 0, r9, c1, c0, 1 @ auxillary control register | 135 | mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register |
136 | mrc p15, 0, r10, c1, c0, 2 @ co-processor access control | 136 | mrc p15, 0, r10, c1, c0, 2 @ co-processor access control |
137 | mrc p15, 0, r11, c1, c0, 0 @ control register | 137 | mrc p15, 0, r11, c1, c0, 0 @ control register |
138 | stmia r0, {r4 - r11} | 138 | stmia r0, {r4 - r11} |
@@ -151,7 +151,7 @@ ENTRY(cpu_v6_do_resume) | |||
151 | mcr p15, 0, r6, c3, c0, 0 @ Domain ID | 151 | mcr p15, 0, r6, c3, c0, 0 @ Domain ID |
152 | mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 | 152 | mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 |
153 | mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 | 153 | mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 |
154 | mcr p15, 0, r9, c1, c0, 1 @ auxillary control register | 154 | mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register |
155 | mcr p15, 0, r10, c1, c0, 2 @ co-processor access control | 155 | mcr p15, 0, r10, c1, c0, 2 @ co-processor access control |
156 | mcr p15, 0, ip, c2, c0, 2 @ TTB control register | 156 | mcr p15, 0, ip, c2, c0, 2 @ TTB control register |
157 | mcr p15, 0, ip, c7, c5, 4 @ ISB | 157 | mcr p15, 0, ip, c7, c5, 4 @ ISB |