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author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-19 16:18:39 -0500 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-19 16:18:39 -0500 |
commit | 59b8175c771040afcd4ad67022b0cc80c216b866 (patch) | |
tree | 4ef5935bee1e342716d49b9d4b99e3fa835526e6 /arch/arm/mm/proc-v6.S | |
parent | 920841d8d1d61bc12b43f95a579a5374f6d98f81 (diff) | |
parent | 3b0eb4a195a124567cd0dd6f700f8388def542c6 (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (117 commits)
[ARM] 4058/2: iop32x: set ->broken_parity_status on n2100 onboard r8169 ports
[ARM] 4140/1: AACI stability add ac97 timeout and retries
[ARM] 4139/1: AACI record support
[ARM] 4138/1: AACI: multiple channel support for IRQ handling
[ARM] 4211/1: Provide a defconfig for ns9xxx
[ARM] 4210/1: base for new machine type "NetSilicon NS9360"
[ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PM
[ARM] 4221/1: S3C2443: DMA support
[ARM] 4220/1: S3C24XX: DMA system initialised from sysdev
[ARM] 4219/1: S3C2443: DMA source definitions
[ARM] 4218/1: S3C2412: fix CONFIG_CPU_S3C2412_ONLY wrt to S3C2443
[ARM] 4217/1: S3C24XX: remove the dma channel show at startup
[ARM] 4090/2: avoid clash between PXA and SA1111 defines
[ARM] 4216/1: add .gitignore entries for ARM specific files
[ARM] 4214/2: S3C2410: Add Armzone QT2410
[ARM] 4215/1: s3c2410 usb device: per-platform vbus_draw
[ARM] 4213/1: S3C2410 - Update definition of ADCTSC_XY_PST
[ARM] 4098/1: ARM: rtc_lock only used with rtc_cmos
[ARM] 4137/1: Add kexec support
[ARM] 4201/1: SMP barriers pair needed for the secondary boot process
...
Fix up conflict due to typedef removal in sound/arm/aaci.h
Diffstat (limited to 'arch/arm/mm/proc-v6.S')
-rw-r--r-- | arch/arm/mm/proc-v6.S | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 7b1843befb9c..eb42e5b94863 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
@@ -14,10 +14,13 @@ | |||
14 | #include <asm/assembler.h> | 14 | #include <asm/assembler.h> |
15 | #include <asm/asm-offsets.h> | 15 | #include <asm/asm-offsets.h> |
16 | #include <asm/elf.h> | 16 | #include <asm/elf.h> |
17 | #include <asm/hardware/arm_scu.h> | ||
18 | #include <asm/pgtable-hwdef.h> | 17 | #include <asm/pgtable-hwdef.h> |
19 | #include <asm/pgtable.h> | 18 | #include <asm/pgtable.h> |
20 | 19 | ||
20 | #ifdef CONFIG_SMP | ||
21 | #include <asm/hardware/arm_scu.h> | ||
22 | #endif | ||
23 | |||
21 | #include "proc-macros.S" | 24 | #include "proc-macros.S" |
22 | 25 | ||
23 | #define D_CACHE_LINE_SIZE 32 | 26 | #define D_CACHE_LINE_SIZE 32 |
@@ -30,6 +33,12 @@ | |||
30 | #define TTB_RGN_WT (2 << 3) | 33 | #define TTB_RGN_WT (2 << 3) |
31 | #define TTB_RGN_WB (3 << 3) | 34 | #define TTB_RGN_WB (3 << 3) |
32 | 35 | ||
36 | #ifndef CONFIG_SMP | ||
37 | #define TTB_FLAGS TTB_RGN_WBWA | ||
38 | #else | ||
39 | #define TTB_FLAGS TTB_RGN_WBWA|TTB_S | ||
40 | #endif | ||
41 | |||
33 | ENTRY(cpu_v6_proc_init) | 42 | ENTRY(cpu_v6_proc_init) |
34 | mov pc, lr | 43 | mov pc, lr |
35 | 44 | ||
@@ -92,9 +101,7 @@ ENTRY(cpu_v6_switch_mm) | |||
92 | #ifdef CONFIG_MMU | 101 | #ifdef CONFIG_MMU |
93 | mov r2, #0 | 102 | mov r2, #0 |
94 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | 103 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id |
95 | #ifdef CONFIG_SMP | 104 | orr r0, r0, #TTB_FLAGS |
96 | orr r0, r0, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable | ||
97 | #endif | ||
98 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB | 105 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
99 | mcr p15, 0, r2, c7, c10, 4 @ drain write buffer | 106 | mcr p15, 0, r2, c7, c10, 4 @ drain write buffer |
100 | mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | 107 | mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 |
@@ -183,8 +190,7 @@ __v6_setup: | |||
183 | /* Set up the SCU on core 0 only */ | 190 | /* Set up the SCU on core 0 only */ |
184 | mrc p15, 0, r0, c0, c0, 5 @ CPU core number | 191 | mrc p15, 0, r0, c0, c0, 5 @ CPU core number |
185 | ands r0, r0, #15 | 192 | ands r0, r0, #15 |
186 | moveq r0, #0x10000000 @ SCU_BASE | 193 | ldreq r0, =SCU_BASE |
187 | orreq r0, r0, #0x00100000 | ||
188 | ldreq r5, [r0, #SCU_CTRL] | 194 | ldreq r5, [r0, #SCU_CTRL] |
189 | orreq r5, r5, #1 | 195 | orreq r5, r5, #1 |
190 | streq r5, [r0, #SCU_CTRL] | 196 | streq r5, [r0, #SCU_CTRL] |
@@ -204,9 +210,7 @@ __v6_setup: | |||
204 | #ifdef CONFIG_MMU | 210 | #ifdef CONFIG_MMU |
205 | mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs | 211 | mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs |
206 | mcr p15, 0, r0, c2, c0, 2 @ TTB control register | 212 | mcr p15, 0, r0, c2, c0, 2 @ TTB control register |
207 | #ifdef CONFIG_SMP | 213 | orr r4, r4, #TTB_FLAGS |
208 | orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable | ||
209 | #endif | ||
210 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | 214 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
211 | #endif /* CONFIG_MMU */ | 215 | #endif /* CONFIG_MMU */ |
212 | adr r5, v6_crval | 216 | adr r5, v6_crval |