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author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-02 18:04:12 -0400 |
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committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-02 18:04:12 -0400 |
commit | a8c4c20dfa8b28a3c99e33c639d9c2ea5657741e (patch) | |
tree | 887b64d29b5a46d9ab2ca1267d8a2f05b5845561 /arch/arm/mm/proc-v6.S | |
parent | 168d04b3b4de7723eb73b3cffc9cb75224e0f393 (diff) | |
parent | 2dc7667b9d0674db6572723356fe3857031101a4 (diff) |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
[ARM] 3541/2: workaround for PXA27x erratum E7
[ARM] nommu: provide a way for correct control register value selection
[ARM] 3705/1: add supersection support to ioremap()
[ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
[ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
[ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
[ARM] 3703/1: Add help description for ARCH_EP80219
[ARM] 3678/1: MMC: Make OMAP MMC work
[ARM] 3677/1: OMAP: Update H2 defconfig
[ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
[ARM] Add section support to ioremap
[ARM] Fix sa11x0 SDRAM selection
[ARM] Set bit 4 on section mappings correctly depending on CPU
[ARM] 3666/1: TRIZEPS4 [1/5] core
ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
ARM: OMAP: Update dmtimers
ARM: OMAP: Make clock variables static
ARM: OMAP: Fix GPMC compilation when DEBUG is defined
ARM: OMAP: Mux updates for external DMA and GPIO
...
Diffstat (limited to 'arch/arm/mm/proc-v6.S')
-rw-r--r-- | arch/arm/mm/proc-v6.S | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index ca13d4d05f65..6f72549f8843 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
@@ -212,11 +212,11 @@ __v6_setup: | |||
212 | orr r0, r0, #(0xf << 20) | 212 | orr r0, r0, #(0xf << 20) |
213 | mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP | 213 | mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP |
214 | #endif | 214 | #endif |
215 | adr r5, v6_crval | ||
216 | ldmia r5, {r5, r6} | ||
215 | mrc p15, 0, r0, c1, c0, 0 @ read control register | 217 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
216 | ldr r5, v6_cr1_clear @ get mask for bits to clear | ||
217 | bic r0, r0, r5 @ clear bits them | 218 | bic r0, r0, r5 @ clear bits them |
218 | ldr r5, v6_cr1_set @ get mask for bits to set | 219 | orr r0, r0, r6 @ set them |
219 | orr r0, r0, r5 @ set them | ||
220 | mov pc, lr @ return to head.S:__ret | 220 | mov pc, lr @ return to head.S:__ret |
221 | 221 | ||
222 | /* | 222 | /* |
@@ -225,12 +225,9 @@ __v6_setup: | |||
225 | * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced | 225 | * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced |
226 | * 0 110 0011 1.00 .111 1101 < we want | 226 | * 0 110 0011 1.00 .111 1101 < we want |
227 | */ | 227 | */ |
228 | .type v6_cr1_clear, #object | 228 | .type v6_crval, #object |
229 | .type v6_cr1_set, #object | 229 | v6_crval: |
230 | v6_cr1_clear: | 230 | crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c |
231 | .word 0x01e0fb7f | ||
232 | v6_cr1_set: | ||
233 | .word 0x00c0387d | ||
234 | 231 | ||
235 | .type v6_processor_functions, #object | 232 | .type v6_processor_functions, #object |
236 | ENTRY(v6_processor_functions) | 233 | ENTRY(v6_processor_functions) |
@@ -269,6 +266,10 @@ __v6_proc_info: | |||
269 | PMD_SECT_CACHEABLE | \ | 266 | PMD_SECT_CACHEABLE | \ |
270 | PMD_SECT_AP_WRITE | \ | 267 | PMD_SECT_AP_WRITE | \ |
271 | PMD_SECT_AP_READ | 268 | PMD_SECT_AP_READ |
269 | .long PMD_TYPE_SECT | \ | ||
270 | PMD_SECT_XN | \ | ||
271 | PMD_SECT_AP_WRITE | \ | ||
272 | PMD_SECT_AP_READ | ||
272 | b __v6_setup | 273 | b __v6_setup |
273 | .long cpu_arch_name | 274 | .long cpu_arch_name |
274 | .long cpu_elf_name | 275 | .long cpu_elf_name |