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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-12-13 09:34:43 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-12-13 09:34:43 -0500
commitad1ae2fe7fe68414ef29eab3c87b48841f8b72f2 (patch)
treef23fc22424f874c1295318904b273c08d00654ab /arch/arm/mm/proc-v6.S
parentf06b97ffd1ed7a96d5022d52f795fba8483afb75 (diff)
[ARM] Unuse another Linux PTE bit
L_PTE_ASID is not really required to be stored in every PTE, since we can identify it via the address passed to set_pte_at(). So, create set_pte_ext() which takes the address of the PTE to set, the Linux PTE value, and the additional CPU PTE bits which aren't encoded in the Linux PTE value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v6.S')
-rw-r--r--arch/arm/mm/proc-v6.S30
1 files changed, 16 insertions, 14 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 513c6c28256d..7b1843befb9c 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -103,13 +103,14 @@ ENTRY(cpu_v6_switch_mm)
103 mov pc, lr 103 mov pc, lr
104 104
105/* 105/*
106 * cpu_v6_set_pte(ptep, pte) 106 * cpu_v6_set_pte_ext(ptep, pte, ext)
107 * 107 *
108 * Set a level 2 translation table entry. 108 * Set a level 2 translation table entry.
109 * 109 *
110 * - ptep - pointer to level 2 translation table entry 110 * - ptep - pointer to level 2 translation table entry
111 * (hardware version is stored at -1024 bytes) 111 * (hardware version is stored at -1024 bytes)
112 * - pte - PTE value to store 112 * - pte - PTE value to store
113 * - ext - value for extended PTE bits
113 * 114 *
114 * Permissions: 115 * Permissions:
115 * YUWD APX AP1 AP0 SVC User 116 * YUWD APX AP1 AP0 SVC User
@@ -121,33 +122,34 @@ ENTRY(cpu_v6_switch_mm)
121 * 11x0 0 1 0 r/w r/o 122 * 11x0 0 1 0 r/w r/o
122 * 1111 0 1 1 r/w r/w 123 * 1111 0 1 1 r/w r/w
123 */ 124 */
124ENTRY(cpu_v6_set_pte) 125ENTRY(cpu_v6_set_pte_ext)
125#ifdef CONFIG_MMU 126#ifdef CONFIG_MMU
126 str r1, [r0], #-2048 @ linux version 127 str r1, [r0], #-2048 @ linux version
127 128
128 bic r2, r1, #0x000003f0 129 bic r3, r1, #0x000003f0
129 bic r2, r2, #0x00000003 130 bic r3, r3, #0x00000003
130 orr r2, r2, #PTE_EXT_AP0 | 2 131 orr r3, r3, r2
132 orr r3, r3, #PTE_EXT_AP0 | 2
131 133
132 tst r1, #L_PTE_WRITE 134 tst r1, #L_PTE_WRITE
133 tstne r1, #L_PTE_DIRTY 135 tstne r1, #L_PTE_DIRTY
134 orreq r2, r2, #PTE_EXT_APX 136 orreq r3, r3, #PTE_EXT_APX
135 137
136 tst r1, #L_PTE_USER 138 tst r1, #L_PTE_USER
137 orrne r2, r2, #PTE_EXT_AP1 139 orrne r3, r3, #PTE_EXT_AP1
138 tstne r2, #PTE_EXT_APX 140 tstne r3, #PTE_EXT_APX
139 bicne r2, r2, #PTE_EXT_APX | PTE_EXT_AP0 141 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
140 142
141 tst r1, #L_PTE_YOUNG 143 tst r1, #L_PTE_YOUNG
142 biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK 144 biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
143 145
144 tst r1, #L_PTE_EXEC 146 tst r1, #L_PTE_EXEC
145 orreq r2, r2, #PTE_EXT_XN 147 orreq r3, r3, #PTE_EXT_XN
146 148
147 tst r1, #L_PTE_PRESENT 149 tst r1, #L_PTE_PRESENT
148 moveq r2, #0 150 moveq r3, #0
149 151
150 str r2, [r0] 152 str r3, [r0]
151 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 153 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
152#endif 154#endif
153 mov pc, lr 155 mov pc, lr
@@ -233,7 +235,7 @@ ENTRY(v6_processor_functions)
233 .word cpu_v6_do_idle 235 .word cpu_v6_do_idle
234 .word cpu_v6_dcache_clean_area 236 .word cpu_v6_dcache_clean_area
235 .word cpu_v6_switch_mm 237 .word cpu_v6_switch_mm
236 .word cpu_v6_set_pte 238 .word cpu_v6_set_pte_ext
237 .size v6_processor_functions, . - v6_processor_functions 239 .size v6_processor_functions, . - v6_processor_functions
238 240
239 .type cpu_arch_name, #object 241 .type cpu_arch_name, #object