diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2009-05-30 09:00:18 -0400 |
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committer | Catalin Marinas <catalin.marinas@arm.com> | 2009-05-30 09:00:18 -0400 |
commit | 26584853a44c58f3d6ac7360d697a2ddcd1a3efa (patch) | |
tree | a47156d781c6207d316746a056a81ca82b90d452 /arch/arm/mm/proc-v6.S | |
parent | ee8c9571191e588ede9a220ded807e33c4897d91 (diff) |
Add core support for ARMv6/v7 big-endian
Starting with ARMv6, the CPUs support the BE-8 variant of big-endian
(byte-invariant). This patch adds the core support:
- setting of the BE-8 mode via the CPSR.E register for both kernel and
user threads
- big-endian page table walking
- REV used to rotate instructions read from memory during fault
processing as they are still little-endian format
- Kconfig and Makefile support for BE-8. The --be8 option must be passed
to the final linking stage to convert the instructions to
little-endian
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm/proc-v6.S')
-rw-r--r-- | arch/arm/mm/proc-v6.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 087e239704df..524ddae92595 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
@@ -170,6 +170,9 @@ __v6_setup: | |||
170 | #endif /* CONFIG_MMU */ | 170 | #endif /* CONFIG_MMU */ |
171 | adr r5, v6_crval | 171 | adr r5, v6_crval |
172 | ldmia r5, {r5, r6} | 172 | ldmia r5, {r5, r6} |
173 | #ifdef CONFIG_CPU_ENDIAN_BE8 | ||
174 | orr r6, r6, #1 << 25 @ big-endian page tables | ||
175 | #endif | ||
173 | mrc p15, 0, r0, c1, c0, 0 @ read control register | 176 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
174 | bic r0, r0, r5 @ clear bits them | 177 | bic r0, r0, r5 @ clear bits them |
175 | orr r0, r0, r6 @ set them | 178 | orr r0, r0, r6 @ set them |