diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-26 07:22:12 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-27 05:48:42 -0400 |
commit | 9ca03a21e320a6bf44559323527aba704bcc8772 (patch) | |
tree | c3422c49decfdca220c0088938546c49ee71ba64 /arch/arm/mm/proc-sa1100.S | |
parent | b8ab5397bcbd92e3fd4a9770e0bf59315fa38dab (diff) |
ARM: Factor out common code from cpu_proc_fin()
All implementations of cpu_proc_fin() start by disabling interrupts
and then flush caches. Rather than have every processors proc_fin()
implementation do this, move it out into generic code - and move the
cache flush past setup_mm_for_reboot() (so it can benefit from having
caches still enabled.)
This allows cpu_proc_fin() to become independent of the L1/L2 cache
types, and eventually move the L2 cache flushing into the L2 support
code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-sa1100.S')
-rw-r--r-- | arch/arm/mm/proc-sa1100.S | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 5c47760c2064..7ddc4805bf97 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S | |||
@@ -55,16 +55,12 @@ ENTRY(cpu_sa1100_proc_init) | |||
55 | * - Clean and turn off caches. | 55 | * - Clean and turn off caches. |
56 | */ | 56 | */ |
57 | ENTRY(cpu_sa1100_proc_fin) | 57 | ENTRY(cpu_sa1100_proc_fin) |
58 | stmfd sp!, {lr} | ||
59 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE | ||
60 | msr cpsr_c, ip | ||
61 | bl v4wb_flush_kern_cache_all | ||
62 | mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching | 58 | mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching |
63 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | 59 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
64 | bic r0, r0, #0x1000 @ ...i............ | 60 | bic r0, r0, #0x1000 @ ...i............ |
65 | bic r0, r0, #0x000e @ ............wca. | 61 | bic r0, r0, #0x000e @ ............wca. |
66 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | 62 | mcr p15, 0, r0, c1, c0, 0 @ disable caches |
67 | ldmfd sp!, {pc} | 63 | mov pc, lr |
68 | 64 | ||
69 | /* | 65 | /* |
70 | * cpu_sa1100_reset(loc) | 66 | * cpu_sa1100_reset(loc) |