[ARM] Set bit 4 on section mappings correctly depending on CPU

On some CPUs, bit 4 of section mappings means "update the
cache when written to".  On others, this bit is required to
be one, and others it's required to be zero.  Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.

With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 6 insertions, 0 deletions

diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 0a2107ad4c32..4e2489c3e1cc 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -276,6 +276,9 @@ __sa1100_proc_info:
                 PMD_SECT_CACHEABLE | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
         b       __sa1100_setup
         .long   cpu_arch_name
         .long   cpu_elf_name
@@ -296,6 +299,9 @@ __sa1110_proc_info:
                 PMD_SECT_CACHEABLE | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
         b       __sa1100_setup
         .long   cpu_arch_name
         .long   cpu_elf_name