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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-02 18:04:12 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-02 18:04:12 -0400 |
| commit | a8c4c20dfa8b28a3c99e33c639d9c2ea5657741e (patch) | |
| tree | 887b64d29b5a46d9ab2ca1267d8a2f05b5845561 /arch/arm/mm/proc-sa110.S | |
| parent | 168d04b3b4de7723eb73b3cffc9cb75224e0f393 (diff) | |
| parent | 2dc7667b9d0674db6572723356fe3857031101a4 (diff) | |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
[ARM] 3541/2: workaround for PXA27x erratum E7
[ARM] nommu: provide a way for correct control register value selection
[ARM] 3705/1: add supersection support to ioremap()
[ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
[ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
[ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
[ARM] 3703/1: Add help description for ARCH_EP80219
[ARM] 3678/1: MMC: Make OMAP MMC work
[ARM] 3677/1: OMAP: Update H2 defconfig
[ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
[ARM] Add section support to ioremap
[ARM] Fix sa11x0 SDRAM selection
[ARM] Set bit 4 on section mappings correctly depending on CPU
[ARM] 3666/1: TRIZEPS4 [1/5] core
ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
ARM: OMAP: Update dmtimers
ARM: OMAP: Make clock variables static
ARM: OMAP: Fix GPMC compilation when DEBUG is defined
ARM: OMAP: Mux updates for external DMA and GPIO
...
Diffstat (limited to 'arch/arm/mm/proc-sa110.S')
| -rw-r--r-- | arch/arm/mm/proc-sa110.S | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index 5a760a2c629c..e812246277cf 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S | |||
| @@ -185,11 +185,12 @@ __sa110_setup: | |||
| 185 | #ifdef CONFIG_MMU | 185 | #ifdef CONFIG_MMU |
| 186 | mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 | 186 | mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 |
| 187 | #endif | 187 | #endif |
| 188 | |||
| 189 | adr r5, sa110_crval | ||
| 190 | ldmia r5, {r5, r6} | ||
| 188 | mrc p15, 0, r0, c1, c0 @ get control register v4 | 191 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
| 189 | ldr r5, sa110_cr1_clear | ||
| 190 | bic r0, r0, r5 | 192 | bic r0, r0, r5 |
| 191 | ldr r5, sa110_cr1_set | 193 | orr r0, r0, r6 |
| 192 | orr r0, r0, r5 | ||
| 193 | mov pc, lr | 194 | mov pc, lr |
| 194 | .size __sa110_setup, . - __sa110_setup | 195 | .size __sa110_setup, . - __sa110_setup |
| 195 | 196 | ||
| @@ -199,12 +200,9 @@ __sa110_setup: | |||
| 199 | * ..01 0001 ..11 1101 | 200 | * ..01 0001 ..11 1101 |
| 200 | * | 201 | * |
| 201 | */ | 202 | */ |
| 202 | .type sa110_cr1_clear, #object | 203 | .type sa110_crval, #object |
| 203 | .type sa110_cr1_set, #object | 204 | sa110_crval: |
| 204 | sa110_cr1_clear: | 205 | crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130 |
| 205 | .word 0x3f3f | ||
| 206 | sa110_cr1_set: | ||
| 207 | .word 0x113d | ||
| 208 | 206 | ||
| 209 | __INITDATA | 207 | __INITDATA |
| 210 | 208 | ||
| @@ -255,6 +253,9 @@ __sa110_proc_info: | |||
| 255 | PMD_SECT_CACHEABLE | \ | 253 | PMD_SECT_CACHEABLE | \ |
| 256 | PMD_SECT_AP_WRITE | \ | 254 | PMD_SECT_AP_WRITE | \ |
| 257 | PMD_SECT_AP_READ | 255 | PMD_SECT_AP_READ |
| 256 | .long PMD_TYPE_SECT | \ | ||
| 257 | PMD_SECT_AP_WRITE | \ | ||
| 258 | PMD_SECT_AP_READ | ||
| 258 | b __sa110_setup | 259 | b __sa110_setup |
| 259 | .long cpu_arch_name | 260 | .long cpu_arch_name |
| 260 | .long cpu_elf_name | 261 | .long cpu_elf_name |
