Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
  [ARM] 5300/1: fixup spitz reset during boot
  [ARM] 5295/1: make ZONE_DMA optional
  [ARM] 5239/1: Palm Zire 72 power management support
  [ARM] 5298/1: Drop desc_handle_irq()
  [ARM] 5297/1: [KS8695] Fix two compile-time warnings
  [ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
  [ARM] pxa: allow multi-machine PCMCIA builds
  [ARM] pxa: add preliminary CPUFREQ support for PXA3xx
  [ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
  [ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
  [ARM] pxa/zylonite: add support for USB OHCI
  [ARM] ohci-pxa27x: use ioremap() and offset for register access
  [ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
  [ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
  [ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
  [ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
  [ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
  [ARM] pxa: simplify DMA register definitions
  [ARM] pxa: make additional DCSR bits valid for PXA3xx
  [ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
  ...

Fixed up conflicts in
	arch/arm/mach-versatile/core.c
	sound/soc/pxa/pxa2xx-ac97.c
	sound/soc/pxa/pxa2xx-i2s.c
manually.

1 files changed, 10 insertions, 23 deletions

diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index f2e5884c513a..0fe1f8fc3488 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -22,7 +22,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -80,7 +80,8 @@ ENTRY(cpu_feroceon_proc_fin)
         msr     cpsr_c, ip
         bl      feroceon_flush_kern_cache_all
 
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+        !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
         mov     r0, #0
         mcr     p15, 1, r0, c15, c9, 0          @ clean L2
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
@@ -389,7 +390,8 @@ ENTRY(feroceon_range_cache_fns)
 
         .align  5
 ENTRY(cpu_feroceon_dcache_clean_area)
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+        !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
         mov     r2, r0
         mov     r3, r1
 #endif
@@ -397,7 +399,8 @@ ENTRY(cpu_feroceon_dcache_clean_area)
         add     r0, r0, #CACHE_DLINESIZE
         subs    r1, r1, #CACHE_DLINESIZE
         bhi     1b
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+        !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
 1:      mcr     p15, 1, r2, c15, c9, 1          @ clean L2 entry
         add     r2, r2, #CACHE_DLINESIZE
         subs    r3, r3, #CACHE_DLINESIZE
@@ -446,27 +449,11 @@ ENTRY(cpu_feroceon_switch_mm)
         .align  5
 ENTRY(cpu_feroceon_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext wc_disable=0
         mov     r0, r0
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+        !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
         mcr     p15, 1, r0, c15, c9, 1          @ clean L2 entry
 #endif
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB