diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-11-26 11:24:19 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-02-15 10:22:23 -0500 |
commit | 702b94bff3c50542a6e4ab9a4f4cef093262fe65 (patch) | |
tree | 2ae468b08de2aeb0e65ab3830c40c7a84dbbdb5e /arch/arm/mm/proc-feroceon.S | |
parent | a9c9147eb9b1dba0ce567a41897c7773b4d1b0bc (diff) |
ARM: dma-mapping: remove dmac_clean_range and dmac_inv_range
These are now unused, and so can be removed.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mm/proc-feroceon.S')
-rw-r--r-- | arch/arm/mm/proc-feroceon.S | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 97e1d784f152..53e632343849 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S | |||
@@ -274,7 +274,7 @@ ENTRY(feroceon_range_flush_kern_dcache_area) | |||
274 | * (same as v4wb) | 274 | * (same as v4wb) |
275 | */ | 275 | */ |
276 | .align 5 | 276 | .align 5 |
277 | ENTRY(feroceon_dma_inv_range) | 277 | feroceon_dma_inv_range: |
278 | tst r0, #CACHE_DLINESIZE - 1 | 278 | tst r0, #CACHE_DLINESIZE - 1 |
279 | bic r0, r0, #CACHE_DLINESIZE - 1 | 279 | bic r0, r0, #CACHE_DLINESIZE - 1 |
280 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 280 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -288,7 +288,7 @@ ENTRY(feroceon_dma_inv_range) | |||
288 | mov pc, lr | 288 | mov pc, lr |
289 | 289 | ||
290 | .align 5 | 290 | .align 5 |
291 | ENTRY(feroceon_range_dma_inv_range) | 291 | feroceon_range_dma_inv_range: |
292 | mrs r2, cpsr | 292 | mrs r2, cpsr |
293 | tst r0, #CACHE_DLINESIZE - 1 | 293 | tst r0, #CACHE_DLINESIZE - 1 |
294 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 294 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
@@ -314,7 +314,7 @@ ENTRY(feroceon_range_dma_inv_range) | |||
314 | * (same as v4wb) | 314 | * (same as v4wb) |
315 | */ | 315 | */ |
316 | .align 5 | 316 | .align 5 |
317 | ENTRY(feroceon_dma_clean_range) | 317 | feroceon_dma_clean_range: |
318 | bic r0, r0, #CACHE_DLINESIZE - 1 | 318 | bic r0, r0, #CACHE_DLINESIZE - 1 |
319 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 319 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
320 | add r0, r0, #CACHE_DLINESIZE | 320 | add r0, r0, #CACHE_DLINESIZE |
@@ -324,7 +324,7 @@ ENTRY(feroceon_dma_clean_range) | |||
324 | mov pc, lr | 324 | mov pc, lr |
325 | 325 | ||
326 | .align 5 | 326 | .align 5 |
327 | ENTRY(feroceon_range_dma_clean_range) | 327 | feroceon_range_dma_clean_range: |
328 | mrs r2, cpsr | 328 | mrs r2, cpsr |
329 | cmp r1, r0 | 329 | cmp r1, r0 |
330 | subne r1, r1, #1 @ top address is inclusive | 330 | subne r1, r1, #1 @ top address is inclusive |
@@ -414,8 +414,6 @@ ENTRY(feroceon_cache_fns) | |||
414 | .long feroceon_flush_kern_dcache_area | 414 | .long feroceon_flush_kern_dcache_area |
415 | .long feroceon_dma_map_area | 415 | .long feroceon_dma_map_area |
416 | .long feroceon_dma_unmap_area | 416 | .long feroceon_dma_unmap_area |
417 | .long feroceon_dma_inv_range | ||
418 | .long feroceon_dma_clean_range | ||
419 | .long feroceon_dma_flush_range | 417 | .long feroceon_dma_flush_range |
420 | 418 | ||
421 | ENTRY(feroceon_range_cache_fns) | 419 | ENTRY(feroceon_range_cache_fns) |
@@ -427,8 +425,6 @@ ENTRY(feroceon_range_cache_fns) | |||
427 | .long feroceon_range_flush_kern_dcache_area | 425 | .long feroceon_range_flush_kern_dcache_area |
428 | .long feroceon_range_dma_map_area | 426 | .long feroceon_range_dma_map_area |
429 | .long feroceon_dma_unmap_area | 427 | .long feroceon_dma_unmap_area |
430 | .long feroceon_range_dma_inv_range | ||
431 | .long feroceon_range_dma_clean_range | ||
432 | .long feroceon_range_dma_flush_range | 428 | .long feroceon_range_dma_flush_range |
433 | 429 | ||
434 | .align 5 | 430 | .align 5 |