diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-11-26 07:56:21 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-12-14 09:53:22 -0500 |
commit | 2c9b9c8490b60428fa2d1c64042f7c7caed93940 (patch) | |
tree | c8af289af8c801193eea924db0cd81f09068ddb9 /arch/arm/mm/proc-feroceon.S | |
parent | ccaf5f05b218e5eb41e2f5cdfd26b18dce4a0218 (diff) |
ARM: add size argument to __cpuc_flush_dcache_page
... and rename the function since it no longer operates on just
pages.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-feroceon.S')
-rw-r--r-- | arch/arm/mm/proc-feroceon.S | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index d0d7795200fc..dbc39383e66a 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S | |||
@@ -226,16 +226,17 @@ ENTRY(feroceon_coherent_user_range) | |||
226 | mov pc, lr | 226 | mov pc, lr |
227 | 227 | ||
228 | /* | 228 | /* |
229 | * flush_kern_dcache_page(void *page) | 229 | * flush_kern_dcache_area(void *addr, size_t size) |
230 | * | 230 | * |
231 | * Ensure no D cache aliasing occurs, either with itself or | 231 | * Ensure no D cache aliasing occurs, either with itself or |
232 | * the I cache | 232 | * the I cache |
233 | * | 233 | * |
234 | * - addr - page aligned address | 234 | * - addr - kernel address |
235 | * - size - region size | ||
235 | */ | 236 | */ |
236 | .align 5 | 237 | .align 5 |
237 | ENTRY(feroceon_flush_kern_dcache_page) | 238 | ENTRY(feroceon_flush_kern_dcache_area) |
238 | add r1, r0, #PAGE_SZ | 239 | add r1, r0, r1 |
239 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | 240 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
240 | add r0, r0, #CACHE_DLINESIZE | 241 | add r0, r0, #CACHE_DLINESIZE |
241 | cmp r0, r1 | 242 | cmp r0, r1 |
@@ -246,7 +247,7 @@ ENTRY(feroceon_flush_kern_dcache_page) | |||
246 | mov pc, lr | 247 | mov pc, lr |
247 | 248 | ||
248 | .align 5 | 249 | .align 5 |
249 | ENTRY(feroceon_range_flush_kern_dcache_page) | 250 | ENTRY(feroceon_range_flush_kern_dcache_area) |
250 | mrs r2, cpsr | 251 | mrs r2, cpsr |
251 | add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive | 252 | add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive |
252 | orr r3, r2, #PSR_I_BIT | 253 | orr r3, r2, #PSR_I_BIT |
@@ -372,7 +373,7 @@ ENTRY(feroceon_cache_fns) | |||
372 | .long feroceon_flush_user_cache_range | 373 | .long feroceon_flush_user_cache_range |
373 | .long feroceon_coherent_kern_range | 374 | .long feroceon_coherent_kern_range |
374 | .long feroceon_coherent_user_range | 375 | .long feroceon_coherent_user_range |
375 | .long feroceon_flush_kern_dcache_page | 376 | .long feroceon_flush_kern_dcache_area |
376 | .long feroceon_dma_inv_range | 377 | .long feroceon_dma_inv_range |
377 | .long feroceon_dma_clean_range | 378 | .long feroceon_dma_clean_range |
378 | .long feroceon_dma_flush_range | 379 | .long feroceon_dma_flush_range |
@@ -383,7 +384,7 @@ ENTRY(feroceon_range_cache_fns) | |||
383 | .long feroceon_flush_user_cache_range | 384 | .long feroceon_flush_user_cache_range |
384 | .long feroceon_coherent_kern_range | 385 | .long feroceon_coherent_kern_range |
385 | .long feroceon_coherent_user_range | 386 | .long feroceon_coherent_user_range |
386 | .long feroceon_range_flush_kern_dcache_page | 387 | .long feroceon_range_flush_kern_dcache_area |
387 | .long feroceon_range_dma_inv_range | 388 | .long feroceon_range_dma_inv_range |
388 | .long feroceon_range_dma_clean_range | 389 | .long feroceon_range_dma_clean_range |
389 | .long feroceon_range_dma_flush_range | 390 | .long feroceon_range_dma_flush_range |