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authorKirill A. Shutemov <kirill@shutemov.name>2009-09-25 08:39:47 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-10-02 17:34:32 -0400
commit4fb2847437d871fe579f820ceb18031db3359901 (patch)
treee2015dbc54178dd114eb0c41fa5a29d89dd15b41 /arch/arm/mm/proc-fa526.S
parent6806bfe18fca92e2001538b84cab5f63c5ea4bed (diff)
ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()
Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-fa526.S')
-rw-r--r--arch/arm/mm/proc-fa526.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 08b8a955d5d7..08f5ac237ad4 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -191,7 +191,7 @@ fa526_cr1_set:
191 .type fa526_processor_functions, #object 191 .type fa526_processor_functions, #object
192fa526_processor_functions: 192fa526_processor_functions:
193 .word v4_early_abort 193 .word v4_early_abort
194 .word pabort_noifar 194 .word legacy_pabort
195 .word cpu_fa526_proc_init 195 .word cpu_fa526_proc_init
196 .word cpu_fa526_proc_fin 196 .word cpu_fa526_proc_fin
197 .word cpu_fa526_reset 197 .word cpu_fa526_reset