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authorRussell King <rmk+kernel@arm.linux.org.uk>2009-11-26 11:24:19 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-02-15 10:22:23 -0500
commit702b94bff3c50542a6e4ab9a4f4cef093262fe65 (patch)
tree2ae468b08de2aeb0e65ab3830c40c7a84dbbdb5e /arch/arm/mm/proc-arm926.S
parenta9c9147eb9b1dba0ce567a41897c7773b4d1b0bc (diff)
ARM: dma-mapping: remove dmac_clean_range and dmac_inv_range
These are now unused, and so can be removed. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mm/proc-arm926.S')
-rw-r--r--arch/arm/mm/proc-arm926.S6
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 72a01a4b80ab..75b707c9cce1 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -246,7 +246,7 @@ ENTRY(arm926_flush_kern_dcache_area)
246 * 246 *
247 * (same as v4wb) 247 * (same as v4wb)
248 */ 248 */
249ENTRY(arm926_dma_inv_range) 249arm926_dma_inv_range:
250#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 250#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
251 tst r0, #CACHE_DLINESIZE - 1 251 tst r0, #CACHE_DLINESIZE - 1
252 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 252 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -271,7 +271,7 @@ ENTRY(arm926_dma_inv_range)
271 * 271 *
272 * (same as v4wb) 272 * (same as v4wb)
273 */ 273 */
274ENTRY(arm926_dma_clean_range) 274arm926_dma_clean_range:
275#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 275#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
276 bic r0, r0, #CACHE_DLINESIZE - 1 276 bic r0, r0, #CACHE_DLINESIZE - 1
2771: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2771: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -337,8 +337,6 @@ ENTRY(arm926_cache_fns)
337 .long arm926_flush_kern_dcache_area 337 .long arm926_flush_kern_dcache_area
338 .long arm926_dma_map_area 338 .long arm926_dma_map_area
339 .long arm926_dma_unmap_area 339 .long arm926_dma_unmap_area
340 .long arm926_dma_inv_range
341 .long arm926_dma_clean_range
342 .long arm926_dma_flush_range 340 .long arm926_dma_flush_range
343 341
344ENTRY(cpu_arm926_dcache_clean_area) 342ENTRY(cpu_arm926_dcache_clean_area)