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authorLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 18:04:12 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 18:04:12 -0400
commita8c4c20dfa8b28a3c99e33c639d9c2ea5657741e (patch)
tree887b64d29b5a46d9ab2ca1267d8a2f05b5845561 /arch/arm/mm/proc-arm926.S
parent168d04b3b4de7723eb73b3cffc9cb75224e0f393 (diff)
parent2dc7667b9d0674db6572723356fe3857031101a4 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits) [ARM] 3541/2: workaround for PXA27x erratum E7 [ARM] nommu: provide a way for correct control register value selection [ARM] 3705/1: add supersection support to ioremap() [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency [ARM] 3703/1: Add help description for ARCH_EP80219 [ARM] 3678/1: MMC: Make OMAP MMC work [ARM] 3677/1: OMAP: Update H2 defconfig [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1 [ARM] Add section support to ioremap [ARM] Fix sa11x0 SDRAM selection [ARM] Set bit 4 on section mappings correctly depending on CPU [ARM] 3666/1: TRIZEPS4 [1/5] core ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE ARM: OMAP: Update dmtimers ARM: OMAP: Make clock variables static ARM: OMAP: Fix GPMC compilation when DEBUG is defined ARM: OMAP: Mux updates for external DMA and GPIO ...
Diffstat (limited to 'arch/arm/mm/proc-arm926.S')
-rw-r--r--arch/arm/mm/proc-arm926.S36
1 files changed, 11 insertions, 25 deletions
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 20275967663d..1e89d4080474 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -403,11 +403,11 @@ __arm926_setup:
403 mcr p15, 7, r0, c15, c0, 0 403 mcr p15, 7, r0, c15, c0, 0
404#endif 404#endif
405 405
406 adr r5, arm926_crval
407 ldmia r5, {r5, r6}
406 mrc p15, 0, r0, c1, c0 @ get control register v4 408 mrc p15, 0, r0, c1, c0 @ get control register v4
407 ldr r5, arm926_cr1_clear
408 bic r0, r0, r5 409 bic r0, r0, r5
409 ldr r5, arm926_cr1_set 410 orr r0, r0, r6
410 orr r0, r0, r5
411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
412 orr r0, r0, #0x4000 @ .1.. .... .... .... 412 orr r0, r0, #0x4000 @ .1.. .... .... ....
413#endif 413#endif
@@ -420,12 +420,9 @@ __arm926_setup:
420 * .011 0001 ..11 0101 420 * .011 0001 ..11 0101
421 * 421 *
422 */ 422 */
423 .type arm926_cr1_clear, #object 423 .type arm926_crval, #object
424 .type arm926_cr1_set, #object 424arm926_crval:
425arm926_cr1_clear: 425 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
426 .word 0x7f3f
427arm926_cr1_set:
428 .word 0x3135
429 426
430 __INITDATA 427 __INITDATA
431 428
@@ -459,22 +456,7 @@ cpu_elf_name:
459 456
460 .type cpu_arm926_name, #object 457 .type cpu_arm926_name, #object
461cpu_arm926_name: 458cpu_arm926_name:
462 .ascii "ARM926EJ-S" 459 .asciz "ARM926EJ-S"
463#ifndef CONFIG_CPU_ICACHE_DISABLE
464 .ascii "i"
465#endif
466#ifndef CONFIG_CPU_DCACHE_DISABLE
467 .ascii "d"
468#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
469 .ascii "(wt)"
470#else
471 .ascii "(wb)"
472#endif
473#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
474 .ascii "RR"
475#endif
476#endif
477 .ascii "\0"
478 .size cpu_arm926_name, . - cpu_arm926_name 460 .size cpu_arm926_name, . - cpu_arm926_name
479 461
480 .align 462 .align
@@ -491,6 +473,10 @@ __arm926_proc_info:
491 PMD_BIT4 | \ 473 PMD_BIT4 | \
492 PMD_SECT_AP_WRITE | \ 474 PMD_SECT_AP_WRITE | \
493 PMD_SECT_AP_READ 475 PMD_SECT_AP_READ
476 .long PMD_TYPE_SECT | \
477 PMD_BIT4 | \
478 PMD_SECT_AP_WRITE | \
479 PMD_SECT_AP_READ
494 b __arm926_setup 480 b __arm926_setup
495 .long cpu_arch_name 481 .long cpu_arch_name
496 .long cpu_elf_name 482 .long cpu_elf_name